公开(公告)号：US20150187413A1

公开(公告)日：2015-07-02

申请号：US14595757

申请日：2015-01-13

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Ryan James Goss ,  Antoine Khoueir

IPC: G11C13/00 ,  G11C11/56 ,  G11C29/08

CPC classification number: G11C13/0002 ,  G11C7/04 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/08 ,  G11C2013/0076

Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.

Abstract translation: 测量影响基于电阻的非易失性存储器的存储单元的两个或多个工作负载指示器。 两个或多个工作负载指示符被应用于响应于两个或更多个工作负载指示器预测电阻偏移和/或电阻噪声方差的传递函数。 应用传递函数的结果来移位和/或确定用于影响存储器单元的程序操作和读取操作中的至少一个的阈值电阻。 结果，存储单元的错误率降低。

公开(公告)号：US09058869B2

公开(公告)日：2015-06-16

申请号：US13761301

申请日：2013-02-07

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Antoine Khoueir ,  Ryan James Goss ,  Jon D. Trantham

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/5614 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0033

Abstract: Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells. In response to the activity metric satisfying a threshold, a bias signal is applied to the cells to reverse a resistance shift of the cells.

Abstract translation: 数据被写入基于电阻的非易失性存储器的单元。 自从将数据写入单元格后，会跟踪活动度量。 响应于满足阈值的活动度量，将偏置信号施加到单元以反转单元的电阻偏移。

公开(公告)号：US20150011062A1

公开(公告)日：2015-01-08

申请号：US14264605

申请日：2014-04-29

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Antoine Khoueir ,  YoungPil Kim ,  Rodney Virgil Bowman

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/66825 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/7889

Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

Abstract translation: 存储器阵列，其包括具有通道的第一存储器单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间; 以及具有通道的第二存储单元; 第一绝缘子; 一个浮动门; 第二绝缘体; 以及控制栅极，其中所述第一绝缘体位于所述沟道和所述浮置栅极之间，所述第二绝缘体位于所述浮置栅极和所述控制栅极之间，其中所述第一存储器单元和所述第二存储器单元彼此平行地定位。

公开(公告)号：US20140332748A1

公开(公告)日：2014-11-13

申请号：US13892675

申请日：2013-05-13

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Antoine Khoueir ,  YoungPil Kim ,  Rodney Virgil Bowman

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.

Abstract translation: 存储器件包括一叠层，包括具有连续电绝缘材料层的连续导电材料字线层的多个交替层。 多个通孔垂直延伸穿过堆叠层，并且垂直位线设置在每个通孔内。 开关材料层将垂直位线与层叠层隔开，从而形成RRAM单元阵列。

公开(公告)号：US20140281280A1

公开(公告)日：2014-09-18

申请号：US13802192

申请日：2013-03-13

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Ryan James Goss ,  Jon D. Trantham ,  Antoine Khoueir ,  David Scott Ebsen ,  Mark Allen Gaertner ,  Kevin Gomez

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0688 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.

Abstract translation: 一种装置包括能够耦合到主机接口和存储器装置的控制器。 存储器件包括具有不同最小可寻址数据单元尺寸的两个或更多个非分级非易失性存储器单元。 控制器被配置为经由主机接口至少执行存储在存储设备中的数据对象的工作量指示符。 控制器响应于与所述工作负载指示符对应的所选择的存储器单元的最小可寻址数据单元大小对应的数据对象的工作量指示符来选择一个存储器单元。 响应于该数据对象被存储在选择的存储单元中。

公开(公告)号：US20140226389A1

公开(公告)日：2014-08-14

申请号：US13762979

申请日：2013-02-08

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： David Scott Ebsen ,  Antoine Khoueir ,  Mark Allen Gaertner

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G06F17/30949 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004

Abstract: Parameters indicative of resistance variance of the memory elements are tracked. The resistance variance affects values of data stored in the resistance-based memory elements. A hash function is performed for each memory element. The hash function returns a reference to one of a plurality of counter elements. A value of each counter element is modified in response to the tracked parameter data of the associated memory element. Read operations affecting the memory elements are adjusted based on the values for the associated counter elements.

Abstract translation: 跟踪表示存储元件的电阻变化的参数。 电阻变化影响存储在基于电阻的存储元件中的数据的值。 对每个存储元件执行散列函数。 散列函数返回对多个计数元素之一的引用。 响应于相关联的存储器元件的跟踪参数数据修改每个计数器元件的值。 基于相关计数器元件的值来调整影响存储元件的读取操作。

公开(公告)号：US20140226388A1

公开(公告)日：2014-08-14

申请号：US13762913

申请日：2013-02-08

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Antoine Khoueir ,  Mark Allen Gaertner ,  Ryan James Goss

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0069

Abstract: A data storage device may generally be constructed and operated with at least one variable resistance memory cell configured with non-factory operational parameters by a controller. The non-factory operational parameters are assigned in response to an identified variance from a predetermined threshold in at least one variable resistance memory cell.

Abstract translation: 一般来说，数据存储装置可由至少一个由控制器配置有非工厂操作参数的可变电阻存储单元构成和操作。 响应于在至少一个可变电阻存储器单元中从预定阈值识别的方差来分配非出厂操作参数。