公开(公告)号：US20090186445A1

公开(公告)日：2009-07-23

申请号：US12411900

申请日：2009-03-26

申请人： Kengo AKIMOTO

发明人： Kengo AKIMOTO

IPC分类号： H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78621

摘要： To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.

公开(公告)号：US20080230825A1

公开(公告)日：2008-09-25

申请号：US12037671

申请日：2008-02-26

申请人： Kengo AKIMOTO

发明人： Kengo AKIMOTO

IPC分类号： H01L29/788

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7883

摘要： The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.

摘要翻译： 本发明涉及一种包括半导体层的非易失性半导体存储器件，该半导体层具有设置在源区和漏区之间的源极区，漏极区和沟道形成区; 以及依次层叠在半导体层上的第一绝缘层，第一栅电极，第二绝缘层和第二栅电极。 源区和漏区的部分或全部使用金属硅化物层形成。 第一栅电极包含惰性气体元件。

公开(公告)号：US20120171813A1

公开(公告)日：2012-07-05

申请号：US13417445

申请日：2012-03-12

申请人： Kengo AKIMOTO

发明人： Kengo AKIMOTO

IPC分类号： H01L21/44

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/45 ,  H01L29/78606

摘要： Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive, layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer 113 is in contact with the second conductive layers and barrier layers including aluminum oxide as a main component, whereby diffusion of aluminum atoms to the oxide semiconductor layer is suppressed.

摘要翻译： 薄膜晶体管的电特性和可靠性受到杂质元素扩散到沟道区域的损害。 本发明提供一种薄膜晶体管，其中铝原子不可能扩散到氧化物半导体层。 包括铟，镓和锌的氧化物半导体层的薄膜晶体管包括源极或漏极电极层，其中以包含铝为主要成分的第一导电层和包括高熔点金属材料的第二导电层被堆叠。 氧化物半导体层113与包括氧化铝作为主要成分的第二导电层和阻挡层接触，从而抑制铝原子向氧化物半导体层的扩散。

公开(公告)号：US20110272700A1

公开(公告)日：2011-11-10

申请号：US13185931

申请日：2011-07-19

申请人： Tetsuji YAMAGUCHI ,  Kengo AKIMOTO ,  Hiroki KAYOIJI ,  Toru TAKAYAMA

发明人： Tetsuji YAMAGUCHI ,  Kengo AKIMOTO ,  Hiroki KAYOIJI ,  Toru TAKAYAMA

IPC分类号： H01L29/786

CPC分类号： H01L27/12 ,  H01L27/1248

摘要： An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode. Expansion or shrinkage of a glass substrate during the heat treatment can be prevented from affecting misalignment in patterning since the gate insulating film and the semiconductor film are simultaneously processed into element shapes after the heat treatment.

摘要翻译： 本发明的目的是提供一种薄膜晶体管的制造方法，其能够进行旨在提高栅极绝缘膜的特性的热处理，例如降低界面电平或降低固定电荷，而不会引起不对准的问题 由于玻璃的膨胀或收缩造成图案化。 本发明的薄膜晶体管的制造方法包括以下步骤：在不进行元件隔离的半导体膜上形成至少栅极绝缘膜的状态下进行热处理，同时隔离栅极绝缘膜和 将半导体膜形成为元件结构，形成覆盖露出的半导体膜的侧面的绝缘膜，由此防止半导体膜与栅电极之间的短路。 由于栅极绝缘膜和半导体膜在热处理后同时被加工成元件形状，所以可以防止热处理期间的玻璃基板的膨胀或收缩，从而影响图案中的未对准。

公开(公告)号：US20100163866A1

公开(公告)日：2010-07-01

申请号：US12634084

申请日：2009-12-09

申请人： Kengo AKIMOTO ,  Masashi TSUBUKU

发明人： Kengo AKIMOTO ,  Masashi TSUBUKU

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/12

CPC分类号： H01L33/0041 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： One of factors that increase the contact resistance at the interface between a first semiconductor layer where a channel is formed and source and drain electrode layers is a film with high electric resistance formed by dust or impurity contamination of a surface of a metal material serving as the source and drain electrode layers. As a solution, a first protective layer and a second protective layer including a second semiconductor having a conductivity that is less than or equal to that of the first semiconductor layer is stacked successively over source and drain electrode layers without exposed to air, the stack of films is used for the source and drain electrode layers.

摘要翻译： 增加在形成沟道的第一半导体层与源电极层与漏极电极层之间的界面处的接触电阻的因素之一是具有高电阻的膜，其由作为金属材料的金属材料的表面的灰尘或杂质污染形成 源极和漏极电极层。 作为解决方案，包括导电率小于或等于第一半导体层的导电率的第二半导体的第一保护层和第二保护层在不暴露于空气的情况下在源极和漏极电极层上依次层叠， 膜用于源电极层和漏电极层。

公开(公告)号：US20100117078A1

公开(公告)日：2010-05-13

申请号：US12614786

申请日：2009-11-09

申请人： Hideaki KUWABARA ,  Kengo AKIMOTO ,  Toshinari SASAKI

发明人： Hideaki KUWABARA ,  Kengo AKIMOTO ,  Toshinari SASAKI

IPC分类号： H01L29/786 ,  H01L29/12 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/24 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78696

摘要： An object is to increase field effect mobility of a thin film transistor including an oxide semiconductor. Another object is to stabilize electrical characteristics of the thin film transistor. In a thin film transistor including an oxide semiconductor layer, a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor is formed over the oxide semiconductor layer, whereby field effect mobility of the thin film transistor can be increased. Further, by forming a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor between the oxide semiconductor layer and a protective insulating layer of the thin film transistor, change in composition or deterioration in film quality of the oxide semiconductor layer is prevented, so that electrical characteristics of the thin film transistor can be stabilized.

摘要翻译： 目的是增加包括氧化物半导体的薄膜晶体管的场效应迁移率。 另一个目的是稳定薄膜晶体管的电特性。 在包括氧化物半导体层的薄膜晶体管中，在氧化物半导体层上形成具有比氧化物半导体更高的导电性的半导体层或导电层，由此可以提高薄膜晶体管的场效应迁移率。 此外，通过在氧化物半导体层和薄膜晶体管的保护绝缘层之间形成具有比氧化物半导体更高的导电性的半导体层或导电层，防止氧化物半导体层的组成变化或膜质量的劣化 ，使得薄膜晶体管的电特性能够稳定。

公开(公告)号：US20100090217A1

公开(公告)日：2010-04-15

申请号：US12575564

申请日：2009-10-08

申请人： Kengo AKIMOTO

发明人： Kengo AKIMOTO

IPC分类号： H01L29/24 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/45 ,  H01L29/78606

摘要： Electric characteristics and reliability of a thin film transistor are impaired by diffusion of an impurity element into a channel region. The present invention provides a thin film transistor in which aluminum atoms are unlikely to be diffused to an oxide semiconductor layer. A thin film transistor including an oxide semiconductor layer including indium, gallium, and zinc includes source or drain electrode layers in which first conductive layers including aluminum as a main component and second conductive layers including a high-melting-point metal material are stacked. An oxide semiconductor layer 113 is in contact with the second conductive layers and barrier layers including aluminum oxide as a main component, whereby diffusion of aluminum atoms to the oxide semiconductor layer is suppressed.

摘要翻译： 薄膜晶体管的电特性和可靠性受到杂质元素扩散到沟道区域的损害。 本发明提供一种薄膜晶体管，其中铝原子不可能扩散到氧化物半导体层。 包括铟，镓和锌的氧化物半导体层的薄膜晶体管包括源极或漏极电极层，其中以铝为主要成分的第一导电层和包含高熔点金属材料的第二导电层被堆叠。 氧化物半导体层113与包括氧化铝作为主要成分的第二导电层和阻挡层接触，从而抑制铝原子向氧化物半导体层的扩散。

公开(公告)号：US20090239335A1

公开(公告)日：2009-09-24

申请号：US12432403

申请日：2009-04-29

申请人： Kengo AKIMOTO ,  Tatsuya HONDA ,  Norihito SONE

发明人： Kengo AKIMOTO ,  Tatsuya HONDA ,  Norihito SONE

IPC分类号： H01L21/20 ,  H01L21/302

CPC分类号： H01L29/78696 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/428 ,  H01L21/465 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7869

摘要： An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

公开(公告)号：US20110272699A1

公开(公告)日：2011-11-10

申请号：US13186170

申请日：2011-07-19

申请人： Kengo AKIMOTO ,  Hotaka MARUYAMA

发明人： Kengo AKIMOTO ,  Hotaka MARUYAMA

IPC分类号： H01L29/786 ,  H01L21/283 ,  H01L21/336

CPC分类号： H01L21/02672 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/2026 ,  H01L21/3221 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78678

摘要： A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.

摘要翻译： 通过在衬底上形成以铝作为主要成分的第一导电层形成栅电极，形成由不同于在第一导电层上形成第一导电层的材料制成的材料制成的第二导电层; 以及图案化第一导电层和第二导电层。 此外，第一导电层包括选自碳，铬，钽，钨，钼，钛，硅和镍中的一种或多种。 并且第二导电层包括选自铬，钽，钨，钼，钛，硅和镍中的一种或多种，​​或这些材料的氮化物。

公开(公告)号：US20100279474A1

公开(公告)日：2010-11-04

申请号：US12768205

申请日：2010-04-27

申请人： Kengo AKIMOTO ,  Daisuke KAWAE

发明人： Kengo AKIMOTO ,  Daisuke KAWAE

IPC分类号： H01L21/336

CPC分类号： H01L27/1225 ,  H01L27/1214 ,  H01L29/7869

摘要： A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer.

摘要翻译： 在薄膜晶体管的氧化物半导体层上设置的栅电极的形成与氧化物半导体层的图案化一起进行。