公开(公告)号：US11289424B2

公开(公告)日：2022-03-29

申请号：US16655260

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065

Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.

公开(公告)号：US20210407942A1

公开(公告)日：2021-12-30

申请号：US17232528

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chih-Hang Tung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

公开(公告)号：US11211336B2

公开(公告)日：2021-12-28

申请号：US16671188

申请日：2019-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/78

Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure. Furthermore, methods for fabricating the integrated fan-out package are also provided.

公开(公告)号：US11195816B2

公开(公告)日：2021-12-07

申请号：US16518992

申请日：2019-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure. The third redistribution structure is disposed over and electrically connected to the second redistribution structure, wherein a linewidth of the third redistribution structure is larger than a linewidth of the second redistribution structure.

公开(公告)号：US20210340008A1

公开(公告)日：2021-11-04

申请号：US17379119

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: B81C1/00 ,  B81B7/00

Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.

公开(公告)号：US20210159139A1

公开(公告)日：2021-05-27

申请号：US16942750

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee ,  Po-Fan Lin

IPC: H01L23/36 ,  H01L23/04 ,  H05K7/20

Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.

公开(公告)号：US10985101B2

公开(公告)日：2021-04-20

申请号：US16354105

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies.

公开(公告)号：US10784227B2

公开(公告)日：2020-09-22

申请号：US16578358

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/42 ,  H01L23/31 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor package. The method may be performed by attaching a first thermal conductivity layer to an upper surface of a first chip, and attaching a second thermal conductivity layer to an upper surface of a second chip. A first support substrate is attached to lower surfaces of the first chip and the second chip. A molding compound is formed over the first support substrate and laterally surrounds the first chip and the second chip. The first support substrate is replaced with a package substrate after forming the molding compound over the first support substrate.

公开(公告)号：US20200266160A1

公开(公告)日：2020-08-20

申请号：US16869573

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00 ,  H01Q1/22 ,  H01L21/683 ,  H01Q21/00

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

公开(公告)号：US10651137B2

公开(公告)日：2020-05-12

申请号：US16043107

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/66 ,  H01L23/538 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00 ,  H01Q1/22 ,  H01Q21/00

Abstract: A method of manufacturing a package structure is provided with the following steps, providing a first die, a second die and a third die; forming a first redistribution layer located on and electrically coupled to the first die, the second die and the third die; and forming an antenna located on and electrically coupled to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna.