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公开(公告)号：US20110215437A1
公开(公告)日：2011-09-08
申请号：US13102007
申请日：2011-05-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L29/06
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译： 公开了图案化半导体结构的方法。 该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。 在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。 通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。 使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。 复合材料层包括在层内由直边限定的离散块中的不同材料。
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公开(公告)号：US20110183481A1
公开(公告)日：2011-07-28
申请号：US13080903
申请日：2011-04-06
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
摘要翻译： 公开了一种结合外延沉积的源/漏半导体膜的晶体管和用于形成晶体管的方法。 晶体蚀刻用于在硅衬底中的沟道区和沟槽隔离区之间形成凹陷。 每个凹部具有与沟道区相邻的第一轮廓和具有与沟槽隔离区相邻的第二轮廓的第一侧。 晶体蚀刻确保第二轮廓成角度，使得所有暴露的凹部表面都包含硅。 因此，可以通过外延沉积而不形成凹坑来填充凹部。 可以使用附加的工艺步骤来确保凹部的第一侧形成有增强通道区域中的期望应力的不同轮廓。
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公开(公告)号：US07943474B2
公开(公告)日：2011-05-17
申请号：US12391631
申请日：2009-02-24
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L28/91
摘要： A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode.An upper electrode is then formed on the conformal dielectric layer. The forming of the upper electrode may include a conformal deposition of metal nitride layer, and a non-conformal deposition of an electrically conductive material atop the metal nitride layer, in which the electrically conductive material encloses the at least one trench.
摘要翻译： 通过首先在半导体衬底中形成至少一个沟槽来提供形成存储器件的方法。 接下来，在至少一个沟槽中形成下电极，之后在下电极上形成保形电介质层。 然后在保形电介质层上形成上电极。 上电极的形成可以包括金属氮化物层的共形沉积，以及金属氮化物层顶部的导电材料的非共形沉积，其中导电材料包围至少一个沟槽。
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公开(公告)号：US07868461B2
公开(公告)日：2011-01-11
申请号：US12478105
申请日：2009-06-04
申请人： Haining Yang , Thomas W. Dyer
发明人： Haining Yang , Thomas W. Dyer
IPC分类号： H01L29/40 , H01L21/336
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.
摘要翻译： 本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构 并且将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。 导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。
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公开(公告)号：US07863693B2
公开(公告)日：2011-01-04
申请号：US12013622
申请日：2008-01-14
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/02
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.
摘要翻译： 本发明的实施例提供一种形成与半导体器件接触的导电柱的方法。 该方法包括形成覆盖半导体器件的保护层; 选择性地将开口向下蚀刻通过保护层到达半导体器件的接触区域，该开口远离半导体器件的保护区域; 并用导电材料填充开口以形成导电柱。 一个实施例还可以包括直接在半导体器件的顶部上形成电介质衬垫，以及在电介质衬垫的顶部上形成保护层。 本发明的实施例还提供由其制成的半导体器件。
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公开(公告)号：US07718993B2
公开(公告)日：2010-05-18
申请号：US12108574
申请日：2008-04-24
IPC分类号： H01L31/00
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译： 与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。 本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。 由于使用了常规处理，所以图案具有圆角的固有限制。 使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。
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公开(公告)号：US20100065922A1
公开(公告)日：2010-03-18
申请号：US12626496
申请日：2009-11-25
IPC分类号： H01L29/78
CPC分类号： H01L29/6656 , H01L21/76232 , H01L21/823481 , H01L21/823878 , H01L29/165 , H01L29/41775 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.
摘要翻译： 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。 移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。 在衬套上形成填充材料。 填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。
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公开(公告)号：US07666721B2
公开(公告)日：2010-02-23
申请号：US11308292
申请日：2006-03-15
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/0653 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
摘要翻译： 提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。 具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分 从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。 可以在SOI衬底中形成一个或多个场效应晶体管（FET）。 例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。
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89.发明授权公开(公告)号：US07635899B2
公开(公告)日：2009-12-22
申请号：US11622057
申请日：2007-01-11
IPC分类号： H01L27/092
CPC分类号： H01L21/823878 , H01L21/76227 , H01L21/76237
摘要： A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surface of the substrate and a partial STI trench is etched in the upper portion of the substrate followed by etching to form a full STI trench. Boron is implanted in a lower area of the full STI trench forming an implant area which is anodized to form a porous silicon region, which is then oxidized to form a oxidized region. A dielectric layer is formed over the silicon nitride layer filling the full STI trench to provide, after etching, at least two electrical component areas on the top surface of the substrate having the full STI trench therebetween.
摘要翻译： 公开了一种用于在CMOS（互补金属氧化物半导体）半导体制造期间在衬底中形成STI（浅沟槽隔离）的方法，其包括提供至少两个包括掺杂剂的阱。 衬底层可以形成在衬底的顶表面上，并且在衬底的上部蚀刻部分STI沟槽，然后蚀刻以形成完整的STI沟槽。 硼被植入整个STI沟槽的下部区域，形成一个阳极氧化以形成多孔硅区域的植入区域，然后被氧化形成氧化区域。 在填充整个STI沟槽的氮化硅层上形成介电层，在蚀刻之后，在衬底的顶表面上提供至少两个具有全部STI沟槽的电气部件区域。
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公开(公告)号：US20090236685A1
公开(公告)日：2009-09-24
申请号：US12478105
申请日：2009-06-04
申请人： Haining Yang , Thomas W. Dyer
发明人： Haining Yang , Thomas W. Dyer
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device comprises a first conductive interconnect structure that is embedded in the isolation region and connects the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first conductive interconnect structure cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof. The conductive interconnect preferably comprises doped polysilicon and can be formed by processing steps including photolithographic patterning, etching, and polysilicon deposition.
摘要翻译： 本发明涉及一种半导体器件，其包括第一和第二有源器件区域，其位于半导体衬底中并且通过其间的隔离区彼此隔离，而半导体器件包括嵌入在隔离中的第一导电互连结构 并且将第一有源器件区域与第二有源器件区域连接。 半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一导电互连结构将SRAM单元的下拉晶体管与其上拉晶体管交叉连接。 导电互连优选地包括掺杂多晶硅，并且可以通过包括光刻图案，蚀刻和多晶硅沉积的处理步骤形成。
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