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    SEMICONDUCTOR MEMORY DEVICE
    82.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20090022001A1

    公开(公告)日：2009-01-22

    申请号：US12281271

    申请日：2006-03-01

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.

    摘要翻译： 通过与设置为OFF的存储晶体管并行地激活字线和位线，控制充电线，字线和位线的电位条件，使得身体区域的电位增加一个 在存储晶体管导通的期间内，从连接节点流向身体区域的漏电流。

    Semiconductor Memory Device
    83.
    发明申请
    Semiconductor Memory Device 有权
    半导体存储器件

    公开(公告)号：US20080251860A1

    公开(公告)日：2008-10-16

    申请号：US10593275

    申请日：2005-06-03

    申请人： Fukashi Morishita ,  Kazutami Arimoto

    发明人： Fukashi Morishita ,  Kazutami Arimoto

    IPC分类号： H01L27/088

    CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

    摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

    摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

    Semiconductor memory device and manufacturing method of the same
    84.
    发明申请
    Semiconductor memory device and manufacturing method of the same 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20080023743A1

    公开(公告)日：2008-01-31

    申请号：US11905002

    申请日：2007-09-27

    申请人： Masakazu Hirose ,  Fukashi Morishita

    发明人： Masakazu Hirose ,  Fukashi Morishita

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10873 ,  G11C11/404 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0218 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78612

    摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

    摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。

    Semiconductor device
    85.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060285576A1

    公开(公告)日：2006-12-21

    申请号：US11452317

    申请日：2006-06-14

    申请人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

    发明人： Takayuki Gyoten ,  Fukashi Morishita ,  Katsumi Dosaka

    IPC分类号： G01K7/00 ,  H05B1/02

    CPC分类号： G01K7/01

    摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.

    摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。

    Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage
    86.
    发明申请
    Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage 失效
    内部电源电压发生电路，可以抑制外部电源电压下限附近的内部电源电压的降低

    公开(公告)号：US20050280465A1

    公开(公告)日：2005-12-22

    申请号：US11210845

    申请日：2005-08-25

    申请人： Fukashi Morishita

    发明人： Fukashi Morishita

    IPC分类号： H02J1/00 ,  G05F1/46 ,  G05F3/24 ,  G11C11/407 ,  H05B37/02

    CPC分类号： G05F1/465

    摘要： An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

    摘要翻译： 内部电源电压产生电路包括主放大器，该主放大器根据来自基准电压产生电路的参考电压和内部电源电压之间的差，从外部电源节点向内部电源线提供电流 内部电源线。 根据外部电源电压和参考电压之间的差异，通过电平调整电路调整主放大器的电流供给量。 内部电源电压产生电路可以抑制差分电源电压的下限区域附近的内部电源电压的降低。

    Semiconductor memory device with circuit executing burn-in testing
    88.
    发明授权
    Semiconductor memory device with circuit executing burn-in testing 失效
    具有执行老化测试的电路的半导体存储器件

    公开(公告)号：US06704231B1

    公开(公告)日：2004-03-09

    申请号：US10397211

    申请日：2003-03-27

    申请人： Fukashi Morishita ,  Mitsuya Kinoshita

    发明人： Fukashi Morishita ,  Mitsuya Kinoshita

    IPC分类号： G11C700

    CPC分类号： G11C29/12005 ,  G11C29/12 ,  G11C2029/1204

    摘要： A semiconductor memory device includes an isolation unit isolating a bit line in a first region including a memory cell formed of a thick film transistor and a second region including a sense amplifier formed of a thin film transistor. Voltage supply lines are provided corresponding to respective regions. In a test mode, the isolation unit isolates the two regions. A voltage for testing is supplied from the voltage supply line. Thus, a voltage for testing corresponding to a thick film transistor and a thin film transistor can be supplied to allow efficient execution of a burn-in test.

    摘要翻译： 半导体存储器件包括隔离单元，隔离包括由厚膜晶体管形成的存储单元的第一区域和包括由薄膜晶体管形成的读出放大器的第二区域的位线。 对应于各个区域提供电压供应线。 在测试模式下，隔离单元隔离两个区域。 用于测试的电压从电源线供应。 因此，可以提供与厚膜晶体管和薄膜晶体管相对应的用于测试的电压，以有效地执行老化测试。

    Voltage down converter allowing supply of stable internal power supply voltage
    89.
    发明授权
    Voltage down converter allowing supply of stable internal power supply voltage 失效
    降压转换器允许提供稳定的内部电源电压

    公开(公告)号：US06407538B1

    公开(公告)日：2002-06-18

    申请号：US09793594

    申请日：2001-02-27

    申请人： Mitsuya Kinoshita ,  Fukashi Morishita

    发明人： Mitsuya Kinoshita ,  Fukashi Morishita

    IPC分类号： G05F316

    CPC分类号： G05F1/465

    摘要： A voltage down converter includes a first voltage down converting circuit and a second voltage down converting circuit. The first voltage down converting circuit supplies an internal power supply voltage VCCS1 to an internal circuit only during a period T when the internal power supply voltage VCCS1 falls below a predetermined voltage according to a signal DCE. In the first voltage down converting circuit, P channel MOS transistors are selectively activated according to the levels of the plurality of voltages, and a voltage down converting partial circuit supplies a current of an amount corresponding to the level of the external power supply voltage VCC to a power supply node. As a result, even during the period T, the internal power supply voltage can be maintained at a level of the reference voltage.

    摘要翻译： 降压转换器包括第一降压转换电路和第二降压转换电路。 第一降压转换电路仅在内部电源电压VCCS1根据信号DCE下降到预定电压以下的时段T期间将内部电源电压VCCS1提供给内部电路。 在第一降压转换电路中，根据多个电压的电平选择性地激活P沟道MOS晶体管，并且降压转换部分电路将对应于外部电源电压VCC的电平的电流提供给 电源节点。 结果，即使在周期T期间，也可以将内部电源电压维持在基准电压的水平。

    Semiconductor device including voltage down converter allowing tuning in short period of time and reduction of chip area
    90.
    发明授权
    Semiconductor device including voltage down converter allowing tuning in short period of time and reduction of chip area 失效
    包括电压降低转换器的半导体器件允许在短时间内调谐并减少芯片面积

    公开(公告)号：US06331962B1

    公开(公告)日：2001-12-18

    申请号：US09489474

    申请日：2000-01-21

    申请人： Mako Kobayashi ,  Fukashi Morishita

    发明人： Mako Kobayashi ,  Fukashi Morishita

    IPC分类号： G05F302

    CPC分类号： G11C11/4074

    摘要： When a tuning mode signal VTUNE is activated, control clock signal TCLK is output, and counter counts up tuning signals TSIG1 to TSIG4. Tuning circuits render conductive the terminals of respective transistors, and reference potential Vref lowers in accordance with the reduction in the resistance value. When reference potential Vref attains equal to the external reference potential Ext.Vref, differential amplifier circuit stops output of the control clock signal TCLK In accordance with the plurality of the determined tuning signals TSIG1 to TSIG4, fuse elements inside the tuning circuits are programmed.

    摘要翻译： 当调谐模式信号VTUNE被激活时，输出控制时钟信号TCLK，并且计数器对调谐信号TSIG1至TSIG4进行计数。 调谐电路使各个晶体管的端子导通，并且参考电位Vref根据电阻值的降低而降低。 当参考电位Vref达到等于外部参考电位Ext.Vref时，差分放大器电路停止控制时钟信号TCLK的输出。根据多个确定的调谐信号TSIG1至TSIG4，编程调谐电路内的熔丝元件。