公开(公告)号：US5658131A

公开(公告)日：1997-08-19

申请号：US404874

申请日：1995-03-16

申请人： Yasushi Aoki ,  Takeshi Ohba ,  Yukihisa Ishii ,  Hiroyuki Matsuo

发明人： Yasushi Aoki ,  Takeshi Ohba ,  Yukihisa Ishii ,  Hiroyuki Matsuo

IPC分类号： B60T13/46 ,  B60T17/02 ,  B60T17/22 ,  F04B49/02 ,  F04B49/10 ,  F04B49/06

CPC分类号： F04B49/10 ,  B60T13/46 ,  B60T17/02 ,  F04B49/022 ,  F04B2205/063

摘要： An electric pump is turned ON and OFF by a main drive circuit including a negative pressure sensor for detecting a negative pressure in an accumulator, a first relay and a control device, and also turned ON and OFF by a back-up drive circuit including a negative pressure switch for detecting a negative pressure in an accumulator, and a second relay. For a period from the starting of the electric pump by the back-up drive circuit to the stopping of the electric pump by the main drive circuit, there is a period during which the electric pump is being driven only by the back-up drive circuit and a period during which the electric pump is being driven only by the main drive circuit. For each of these periods, a trouble of the main drive circuit and/or the back-up drive circuit can be determined by reference to a check signal indicative of the operational state of the electric pump. Thus, it is possible to reliably detect a trouble with the driving of the electric pump connected to the accumulator.

摘要翻译： 电动泵通过包括用于检测蓄电池，第一继电器和控制装置中的负压的负压传感器的主驱动电路接通和断开，并且还通过包括 用于检测蓄能器中的负压的负压开关和第二继电器。 在通过辅助驱动电路从电动泵启动到主驱动电路停止电动泵的期间，电动泵仅由备用驱动电路驱动 以及电动泵仅由主驱动电路驱动的期间。 对于这些周期中的每一个，主驱动电路和/或备用驱动电路的故障可以通过参考表示电动泵的运行状态的检查信号来确定。 因此，可以可靠地检测连接到蓄电池的电动机的驱动的故障。

公开(公告)号：US5576969A

公开(公告)日：1996-11-19

申请号：US207663

申请日：1994-03-09

申请人： Yasushi Aoki ,  Minoru Kayano ,  Kousuke Uno

发明人： Yasushi Aoki ,  Minoru Kayano ,  Kousuke Uno

IPC分类号： G06F17/50 ,  H01L27/02 ,  G06F17/10

CPC分类号： H01L27/0207 ,  G06F17/5068

摘要： For functional blocks of an IC, each functional block comprising a plurality of macroblocks, each macroblock comprising a plurality of basic cells, a mask pattern is patterned in accordance with a layout design by using its connection data of the macroblocks in each functional block and its placement data of the basic cells in each functional block. Use of the placement data in addition to the connection data makes it possible to regularly and systematically arrange the basic cells in each functional block to achieve shortest possible connections in each fundamental block and a narrowest possible area of each functional block. In order to put a CPU in operation of patterning the mask pattern, an operating system comprises for read by the CPU first and second memories loaded with the connection and the placement data, respectively.

摘要翻译： 对于IC的功能块，每个功能块包括多个宏块，每个宏块包括多个基本单元，掩模图案根据布局设计通过使用其每个功能块中的宏块的连接数据及其 每个功能块中的基本单元的放置数据。 除了连接数据之外，使用放置数据使得可以定期和系统地布置每个功能块中的基本单元，以实现每个基本块中的最短可能连接和每个功能块的最窄可能区域。 为了使CPU对图案化掩模图案进行操作，操作系统包括分别由加载有连接和布局数据的CPU的第一和第二存储器读取。

公开(公告)号：US5469081A

公开(公告)日：1995-11-21

申请号：US292142

申请日：1994-08-08

申请人： Satomi Horita ,  Yasushi Aoki ,  Masahiro Wakana ,  Hiroshi Okamoto ,  Kiyohiko Chiba ,  Shizue Daikoku

发明人： Satomi Horita ,  Yasushi Aoki ,  Masahiro Wakana ,  Hiroshi Okamoto ,  Kiyohiko Chiba ,  Shizue Daikoku

IPC分类号： H03K19/017 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018507

摘要： An interconnection circuit having a circuit portion which is provided in one of two integrated semiconductors to be connected, for limiting the amplitude in voltage of the signal output from said one circuit, and another circuit portion which is provided in the other one of the two circuits, for discriminating the logic level of the signal input thereinto based on a threshold level set at an intermediate level between said amplitude. The amplitude of the logic signal transferred across the two circuits is thus compressed, thereby deereasing delay time for the signal to transfer between the two circuits.

摘要翻译： 一种互连电路，具有设置在要连接的两个集成半导体中的一个中的电路部分，用于限制从所述一个电路输出的信号的电压幅度，以及设置在两个电路中的另一个中的另一个电路部分 用于基于在所述幅度之间的中间电平设置的阈值电平来区分其中输入的信号的逻辑电平。 因此，两个电路之间传输的逻辑信号的幅度被压缩，从而消除了在两个电路之间传输信号的延迟时间。

公开(公告)号：US5467041A

公开(公告)日：1995-11-14

申请号：US264617

申请日：1994-06-23

申请人： Mitsuo Baba ,  Yasushi Aoki

发明人： Mitsuo Baba ,  Yasushi Aoki

IPC分类号： H03K5/13 ,  H03K5/131 ,  H03L7/00

CPC分类号： H03K5/131 ,  H03K5/133

摘要： A variable delay buffer circuit composed of a cascade of variable delay buffers, which realizes a delay in response to a delay control signal without any glitches. The delay buffers each have a selector circuit for selecting one of an input signal and a delayed signal produced by delaying in time the input signal in response to a delaying information. The delay buffers each contains a first control means and an output means. The first control means controls a timing of a input of the delaying information into the selector circuit in response to an external control signal. The output means outputs the control signal to by synchronized with an output signal from the selector circuit. Preferably, the first control means contains a latching means for latching the delay information and a second control means for controlling a timing in output of the delay information from the latching means in response to the control signal.

摘要翻译： 由可变延迟缓冲器的级联组成的可变延迟缓冲电路，其实现响应于延迟控制信号而没有毛刺的延迟。 延迟缓冲器各自具有选择器电路，用于响应于延迟信息来选择输入信号和延迟信号中的一个，该延迟信号是通过延迟输入信号而产生的。 延迟缓冲器各自包含第一控制装置和输出装置。 第一控制装置响应于外部控制信号控制延迟信息输入到选择器电路的定时。 输出装置通过与来自选择器电路的输出信号同步地输出控制信号。 优选地，第一控制装置包括用于锁存延迟信息的锁存装置和用于响应于控制信号控制来自锁存装置的延迟信息的输出定时的第二控制装置。

公开(公告)号：US5453990A

公开(公告)日：1995-09-26

申请号：US49413

申请日：1993-04-20

申请人： Yasushi Aoki ,  Akihiro Shiratori

发明人： Yasushi Aoki ,  Akihiro Shiratori

IPC分类号： H04M3/22 ,  G01R31/3185 ,  H04Q1/24 ,  H04Q3/52 ,  G06F11/00 ,  G01R31/28

CPC分类号： G01R31/318516

摘要： Switching circuits are connected between data input lines to and data output lines to connect switch paths between them. A two-input selector is connected to each of the data input lines to supply a data input signal or a test signal to the switching circuits. The selection of the two signals depends on whether the data input line is being used or not. The switch path connections in the switching circuits are controlled by the switching control circuits. Normally, a particular switch path is connected, but while testing, all the switch paths of an unoperated switching circuit which is not normally selected, are connected by a test address signal. The outputs of the switching circuits are detected by an error detector and compared with an expected data sequence, which indicates which output of the switching circuits is detected by the error detector.

摘要翻译： 开关电路连接在数据输入线与数据输出线之间，以连接它们之间的开关路径。 两输入选择器连接到每个数据输入线，以将数据输入信号或测试信号提供给开关电路。 两个信号的选择取决于数据输入线是否被使用。 开关电路中的开关路径连接由开关控制电路来控制。 通常，特定的开关路径被连接，但是在测试时，未经常选择的未操作的开关电路的所有开关路径都通过测试地址信号连接。 开关电路的输出由误差检测器检测，并与期望的数据序列进行比较，该期望数据序列指示由误差检测器检测出哪个开关电路的输出。

公开(公告)号：US5313401A

公开(公告)日：1994-05-17

申请号：US552126

申请日：1990-07-13

申请人： Shozo Kasai ,  Yusaku Azuma ,  Yasushi Aoki ,  Makoto Akahira ,  Takeshi Yakou ,  Katsumi Ishihara

发明人： Shozo Kasai ,  Yusaku Azuma ,  Yasushi Aoki ,  Makoto Akahira ,  Takeshi Yakou ,  Katsumi Ishihara

IPC分类号： H05K13/02 ,  H05K13/04 ,  H05K13/08 ,  G06F15/46 ,  H05K3/30

CPC分类号： H05K13/0408 ,  H05K13/021 ,  H05K13/0473 ,  H05K13/08 ,  Y10T29/49124 ,  Y10T29/49133 ,  Y10T29/4914

摘要： A mounting system having a function of picking up one of several different type works from a pickup position where the works having the different types are selectively fed, and of moving a picked up work to an insertion position so as to mount the work on a printed circuit board. The mounting system includes a rotary member arranged to be rotatable, head mechanisms having different types and mounted on the rotary member, the head mechanisms having a number of types corresponding to that of the types of the works, a memory for storing a pickup order and an insertion order in units of types of works, a driver for rotating and stopping the rotary member at predetermined angles, and a control device for preferentially driving the head mechanism to the pickup or insertion position.

摘要翻译： 具有从具有不同类型的作品被选择性地馈送的拾取位置拾取几种不同类型作品中的一种的功能的安装系统，以及将拾取工件移动到插入位置，以便将工件安装在印刷 电路板。 安装系统包括可旋转的旋转构件，具有不同类型并安装在旋转构件上的头部机构，头部机构具有与工件类型相对应的多种类型的类型，用于存储拾取顺序的存储器， 以工件类型为单位的插入顺序，用于以预定角度旋转和停止旋转构件的驱动器，以及用于优先地将头机构驱动到拾取或插入位置的控制装置。

公开(公告)号：US5170074A

公开(公告)日：1992-12-08

申请号：US667873

申请日：1991-03-12

申请人： Yasushi Aoki

发明人： Yasushi Aoki

IPC分类号： H03K3/3562

CPC分类号： H03K3/35625

摘要： A flip-flop of a master-slave type of a CMOS structure having no P channel transistor between nodes of the master flip-flop and of the slave flip-flop is provided. Only one P channel MOS transistor is existent in a route of the current controlling a rise time and a trail time of output signals, so that it is possible to function at a high speed.

摘要翻译： 提供了在主触发器和从触发器的节点之间没有P沟道晶体管的主从型CMOS结构的触发器。 在控制输出信号的上升时间和跟踪时间的电流的路径中仅存在一个P沟道MOS晶体管，使得可以高速运行。

公开(公告)号：US5013937A

公开(公告)日：1991-05-07

申请号：US351346

申请日：1989-05-15

申请人： Yasushi Aoki

发明人： Yasushi Aoki

IPC分类号： H03K19/0948 ,  H03K19/017 ,  H03K19/21

CPC分类号： H03K19/215 ,  H03K19/01707

摘要： An output circuit for a high speed and low power logic circuit is disclosed. The logic circuit performs a logic operation on a plurality of input data signals supplied thereto and produces true and complementary intermediate output signals, the logic high level of the intermediate output signal being lower than a first power voltage and the logic low level thereof being substantially equal to a second power voltage. The output circuit includes a P-channel MOS transistor having a gate supplied with the complementary intermediate output signal, a source connected to a power voltage supplied with the first power voltage and a drain connected to an output terminal, and an N-channel MOS transistor having a gate connected to the power terminal, a source supplied with the true intermediate output signal and a drain connected to the output terminal, and thus produces at the output terminal an output signal having a logic amplitude between the first and second power voltages.

公开(公告)号：US4839897A

公开(公告)日：1989-06-13

申请号：US114302

申请日：1987-10-28

申请人： Yasushi Aoki

发明人： Yasushi Aoki

IPC分类号： H03M7/38 ,  H03M3/04 ,  H04B14/06 ,  H04L29/14

CPC分类号： H04B14/068 ,  H03M3/042

摘要： A fault detecting system is provided for detecting fault of an ADPCM codec for transcoding an input signal between an ADPCM and a PCM to produce a first code converted signal. The ADPCM codec has a data RAM for storing data used for the transcoding and is provided with a data transmitter for transmitting the data. A fault detecting processor receives the data and generates a second code conversion signal from the received data. The fault detecting processor compares the first and the second code converted signals and produces a fault signal when both of the signals are not coincident with each other. The input signal can be supplied to the fault detecting processor directly or as a part of the data transmitted thereto. The fault detecting processor can detect fault of a plurality of ADPCM codecs by a time division fashion. The ADPCM codec and the fault detecting processor may be implemented as similar LSI processors each comprising a transcoding section, a data transmitting/receiving section, and a comparing section.

摘要翻译： 提供故障检测系统，用于检测用于对ADPCM和PCM之间的输入信号进行代码转换的ADPCM编解码器的故障，以产生第一代码转换信号。 ADPCM编解码器具有用于存储用于代码转换的数据的数据RAM，并且具有用于发送数据的数据发送器。 故障检测处理器接收数据并从接收的数据产生第二代码转换信号。 故障检测处理器比较第一和第二代码转换信号，并且当两个信号彼此不一致时产生故障信号。 输入信号可以直接提供给故障检测处理器，也可以作为发送给它的数据的一部分。 故障检测处理器可以通过时分方式检测多个ADPCM编解码器的故障。 ADPCM编解码器和故障检测处理器可以被实现为每个包括代码转换部分，数据发送/接收部分和比较部分的类似LSI处理器。