公开(公告)号：US20100135086A1

公开(公告)日：2010-06-03

申请号：US12326283

申请日：2008-12-02

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L21/28282 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/107 ,  H01L29/78654 ,  H01L29/792

摘要： A method of operating a non-volatile memory cell is described, including pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier and programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier.

摘要翻译： 描述了操作非易失性存储器单元的方法，包括通过双侧偏置（DSB）注入第一类型的载波来预擦除该单元，并通过第二类型的Fowler-Nordheim（FN）隧穿对该单元进行编程 的载体。

公开(公告)号：US07593262B2

公开(公告)日：2009-09-22

申请号：US11637155

申请日：2006-12-12

申请人： Chao-I Wu ,  Ming-Hsiang Hsueh

发明人： Chao-I Wu ,  Ming-Hsiang Hsueh

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.

摘要翻译： 提供了一种用于操作用于使存储器件具有第一阈值电压或第二阈值电压的存储器的方法。 该方法包括以下步骤。 首先，将操作电压施加到存储器件的栅极第一时间段，使得存储器件具有第一阈值电压。 接下来，将相同的工作电压施加到存储器的栅极第二时间段，使得存储器件具有第二阈值电压。 第一时间段的持续时间与第二时间段的持续时间不同。

公开(公告)号：US07590005B2

公开(公告)日：2009-09-15

申请号：US11625236

申请日：2007-01-19

申请人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

发明人： Tzu Hsuan Hsu ,  Chao-I Wu ,  Kuang Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. The programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷捕获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧穿方法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 电荷捕获存储器的编程是使用衬底瞬态热电子注入进行的，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07570514B2

公开(公告)日：2009-08-04

申请号：US11625456

申请日：2007-01-22

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  B82Y10/00 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2216/06

摘要： A method of operating a multi-level cell is provided. The method includes the following the steps. (a) The multi-level cell is operated until a threshold voltage is larger than a pre-programming threshold voltage. And (b) the multi-level cell is operated until the threshold voltage is larger than a target programming threshold voltage and smaller than the pre-programming threshold voltage. Moreover, between the step (a) and the step (b), further comprises (c) A first verification step is performed. If the threshold voltage is smaller than the pre-programming threshold voltage, then repeat the step (a). Furthermore, after the step (b), further comprises (d) a second verification step is performed. If the threshold voltage is larger than the pre-programming threshold voltage, repeat the step (b), and if the threshold voltage is smaller than the target programming threshold voltage, repeat the steps (a)-(d).

摘要翻译： 提供了一种操作多级单元的方法。 该方法包括以下步骤。 （a）操作多电平电池，直到阈值电压大于预编程阈值电压。 和（b）多电平电池被操作直到阈值电压大于目标编程阈值电压并且小于预编程阈值电压。 此外，在步骤（a）和步骤（b）之间还包括（c）执行第一验证步骤。 如果阈值电压小于预编程阈值电压，则重复步骤（a）。 此外，在步骤（b）之后还包括（d）执行第二验证步骤。 如果阈值电压大于预编程阈值电压，则重复步骤（b），如果阈值电压小于目标编程阈值电压，则重复步骤（a） - （d）。

公开(公告)号：US07561470B2

公开(公告)日：2009-07-14

申请号：US11614742

申请日：2006-12-21

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/0491

摘要： The present invention provides a method for applying a double-side-bias operation to a virtual ground array memory composed of a matrix of N-bit memory cells. In a first embodiment, the virtual ground array is programmed by a double-side-bias method which applies the same or similar biasing voltage simultaneously on the source region and drain region of a selected charge trapping memory cell so that the left bit and the right bit of the selected charge trapping memory cell are programmed together. In a second embodiment, the virtual ground array is erased by a double-side-bias method which applies the same or similar biasing voltage simultaneously on source regions and regions of a plurality of charge trapping memory cells in the virtual ground array so that the left bit and the right bit of each charge trapping memory cell are erased together.

摘要翻译： 本发明提供了一种将双面偏置操作应用于由N位存储器单元矩阵组成的虚拟接地阵列存储器的方法。 在第一实施例中，虚拟接地阵列通过双侧偏置方法编程，该方法在所选择的电荷捕获存储器单元的源极区域和漏极区域上同时施加相同或相似的偏置电压，使得左侧位和右侧 所选择的电荷捕获存储单元的位被一起编程。 在第二实施例中，虚拟接地阵列被双侧偏置方法擦除，该方法在虚拟接地阵列中的多个电荷俘获存储器单元的源极区域和区域上同时施加相同或相似的偏置电压，使得左侧 并且每个电荷捕获存储单元的右位被一起擦除。

公开(公告)号：US07486567B2

公开(公告)日：2009-02-03

申请号：US11741917

申请日：2007-04-30

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/0466

摘要： A method of high speed programming and erasing of a charge trapping memory using turn-on-mode assist-charge (TOM-AC) operations. The charge trapping memory includes a charge trapping structure overlying a substrate body with source and drain regions. The charge trapping structure includes a charge trapping layer overlying a dielectric layer. The charge trapping layer has an assist charge site (also referred to as AC-site, AC-side, or a first charge trapping site) and a data site (also referred to as data-side or a second charge trapping site). Initially, to place the charge trapping memory cell in a TOM operation, both the AC-site and the data site of the charge trapping memory cell are erased to a negative threshold voltage level, −Vt, by FN injection, thereby inducing a hole charge induced channel between the source and drain regions.

摘要翻译： 使用接通模式辅助充电（TOM-AC）操作来高速编程和擦除电荷俘获存储器的方法。 电荷俘获存储器包括覆盖衬底主体的电荷捕获结构，源极和漏极区域。 电荷捕获结构包括覆盖介电层的电荷捕获层。 电荷捕获层具有辅助电荷位置（也称为AC位点，AC侧或第一电荷捕获位点）和数据位点（也称为数据侧或第二电荷捕获位点）。 最初，为了将电荷捕获存储单元置于TOM操作中，通过FN注入将电荷俘获存储单元的AC位置和数据位都擦除到负阈值电压-Vt，从而引起空穴电荷 在源极和漏极区之间引起的沟道。

公开(公告)号：US07485531B2

公开(公告)日：2009-02-03

申请号：US11760142

申请日：2007-06-08

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7883 ,  H01L29/7885

摘要： A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked structure and the exposed substrate. A charge storage layer covers over the top and sidewalls of the stacked structure. Also, a pair of auxiliary gates is formed over the substrate beside the charge storage layer, and a gap is between the auxiliary gates and the charge storage layer.

摘要翻译： 提供了一种制造非易失性存储器的方法。 堆叠结构形成在衬底上，堆叠结构在其上具有栅介电层和浮栅。 第一电介质层，第二电介质层和第三电介质层分别形成在层叠结构的顶部和侧壁以及暴露的基板上。 电荷存储层覆盖层叠结构的顶部和侧壁。 此外，在电荷存储层旁边的基板上形成一对辅助栅极，并且在辅助栅极和电荷存储层之间形成间隙。

公开(公告)号：US20080266980A1

公开(公告)日：2008-10-30

申请号：US11741059

申请日：2007-04-27

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/0483 ,  G11C16/10

摘要： Methods are described for double-side-biasing of a NAND memory array device comprising a plurality of charge trapping memory cells for programming and erasing the NAND memory array device. A double-side-biasing method applies a bias voltage simultaneously on a first junction (a source region) and a second junction (a drain region) so that a left bit and a right bit in a charge trapping memory cell can be programmed in parallel or erased in parallel. Random (or selective) bit program and random (or selective) bit erase can be achieved by using a double-side-biasing method on a NAND memory array device for both data and code application. A first type of double-side-biasing method is to program the NAND array with a double-side-bias electron injection. A second type of double-side-biasing method is to erase the NAND array with a double-side-bias hole injection.

摘要翻译： 描述了包括用于对NAND存储器阵列器件进行编程和擦除的多个电荷俘获存储器单元的NAND存储器阵列器件的双侧偏置的方法。 双侧偏置方法在第一结（源极区）和第二结（漏极区）上同时施加偏置电压，使得电荷俘获存储单元中的左位和右位可以并行编程 或并行擦除。 随机（或选择性）位程序和随机（或选择性）位擦除可以通过在NAND存储器阵列器件上使用双侧偏置方法来实现数据和代码应用。 第一种双侧偏置方法是用双侧偏置电子注入对NAND阵列进行编程。 第二种双侧偏置方法是通过双侧偏置空穴注入来擦除NAND阵列。

公开(公告)号：US20080266969A1

公开(公告)日：2008-10-30

申请号：US12169142

申请日：2008-07-08

申请人： Ming-Chang Kuo ,  Chao-I Wu

发明人： Ming-Chang Kuo ,  Chao-I Wu

IPC分类号： G11C16/06 ,  H01L29/792

CPC分类号： G11C16/0475 ,  G11C16/12

摘要： A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

摘要翻译： 提供一种操作具有基板，栅极，电荷俘获层，源极区域和漏极区域的非易失性存储器的方法。 靠近源区的电荷捕获层是辅助电荷区，靠近漏极区的电荷捕获层是数据存储区。 在起诉前，电子注入到辅助电荷区域。 当起动编程操作时，向栅极施加第一电压，将第二电压施加到源极区域，向漏极区域施加第三电压，并向衬底施加第四电压。 第一电压大于第四电压，第三电压大于第二电压，第二电压大于第四电压，以启动通道启动的次级热电子注入以将电子注入数据存储区域。

公开(公告)号：US20080068889A1

公开(公告)日：2008-03-20

申请号：US11530202

申请日：2006-09-08

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11568

摘要： The invention is directed to a NAND memory cell at an initializing state. The NAND memory cell at the initializing state comprises a substrate, a gate, at least two doped regions, a carrier storage element and a plurality of carriers. The substrate has at least two isolation structures formed therein and the isolation structures are parallel to each other. The gate is disposed over the substrate and across the isolation structures. The doped regions are disposed at both sides of the gate in the substrate between the isolation structures respectively. The carrier storage element is disposed between the substrate and the gate. The carriers are disposed in the carrier storage elements and aggregating above the edges of the isolation structures.

摘要翻译： 本发明涉及初始化状态下的NAND存储单元。 初始化状态下的NAND存储单元包括衬底，栅极，至少两个掺杂区域，载流子存储元件和多个载流子。 衬底具有形成在其中的至少两个隔离结构，隔离结构彼此平行。 栅极设置在衬底上并跨越隔离结构。 掺杂区域分别设置在隔离结构之间的衬底中的栅极的两侧。 载体存储元件设置在基板和栅极之间。 载体被布置在载体存储元件中并聚集在隔离结构的边缘上方。