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公开(公告)号：US09086450B2
公开(公告)日：2015-07-21
申请号：US12897150
申请日：2010-10-04
申请人： Min-Tar Liu , Chih-Chiang Chang , Chu-Fu Chen , Ping-Hsiang Huang
发明人： Min-Tar Liu , Chih-Chiang Chang , Chu-Fu Chen , Ping-Hsiang Huang
CPC分类号： G01R31/2884 , G01R27/2605 , H03K17/962
摘要： A capacitor measurement circuit for measuring a capacitance of a test capacitor includes a first transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; and a current-measuring device configured to measure a first charging current and a second charging current of the test capacitors. The first and the second charging currents flow to the test capacitor in opposite directions.
摘要翻译： 用于测量测试电容器的电容的电容器测量电路包括：第一晶体管，其具有耦合在测试电容器的第一电容器板和地之间的第一源极 - 漏极路径; 第二晶体管，其具有耦合在所述测试电容器的第二电容器板和地之间的第二源极 - 漏极路径; 以及电流测量装置，被配置为测量所述测试电容器的第一充电电流和第二充电电流。 第一和第二充电电流以相反的方向流向测试电容器。
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公开(公告)号：US08667349B2
公开(公告)日：2014-03-04
申请号：US13207494
申请日：2011-08-11
申请人： Shang-Chih Hsieh , Chih-Chiang Chang , Chang-Yu Wu
发明人： Shang-Chih Hsieh , Chih-Chiang Chang , Chang-Yu Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.
摘要翻译： 扫描触发器电路包括用于向数据节点提供数据信号的输入级，其中输入级包括耦合到数据节点的晶体管器件的第一和第二堆叠。 第一堆栈在用于输入到数据节点的正常操作模式期间接收数据输入信号，并且第二堆栈在用于输入到数据节点的扫描测试模式期间接收扫描输入信号。 扫描触发器电路还包括直接耦合到数据节点的主锁存器，用于锁存来自输入级的数据信号并输出数据信号; 耦合到主锁存器的输出的从锁存器，用于锁存来自主锁存器的输出并输出该输出; 以及扫描和时钟控制逻辑模块。 扫描和时钟控制逻辑模块控制第一个堆栈，以在正常操作模式下将数据输入信号输入到数据节点。
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公开(公告)号：US20140040836A1
公开(公告)日：2014-02-06
申请号：US13562638
申请日：2012-07-31
申请人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
发明人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
摘要翻译： 除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。 例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。 在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。 例如，第一图案密度和第二图案密度是门密度和/或多密度。 为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。 以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。
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公开(公告)号：US20140027821A1
公开(公告)日：2014-01-30
申请号：US13557479
申请日：2012-07-25
CPC分类号： H01L29/4238 , H01L21/28123 , H01L29/78
摘要： Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
摘要翻译： 除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。 在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。 与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。 因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它被包括在该区域的非边缘内。 例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。
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公开(公告)号：US08552785B2
公开(公告)日：2013-10-08
申请号：US13292124
申请日：2011-11-09
申请人： Ming-Zhang Kuo , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
发明人： Ming-Zhang Kuo , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
IPC分类号： G06F1/04
CPC分类号： H03K3/033
摘要： A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
摘要翻译： 电路包括逻辑门和锁存器。 逻辑门被配置为在第一输入处接收时钟信号。 锁存器被布置在逻辑门的反馈回路中，并被配置为响应于由逻辑门输出的信号和时钟信号而将反馈信号输出到逻辑门的第二输入端。 电路被配置为基于时钟信号的上升沿或下降沿中的一个输出脉冲信号。
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公开(公告)号：US08514000B1
公开(公告)日：2013-08-20
申请号：US13562539
申请日：2012-07-31
IPC分类号： H03K3/00
CPC分类号： H03K3/0375 , H03K3/356156
摘要： Some embodiments relate to a flip-flop having a data input terminal, a data output terminal and a clock terminal. The flip-flop includes a master latch, a slave latch, and an isolation element coupled between the master latch output and slave latch. The isolation element is arranged to isolate capacitive loading seen by the output of the master latch that comes from the slave latch. In some embodiments, the master latch includes one or more drive enhancement elements on its feedforward and feedback paths. The slave latch can also include one or more drive enhancement elements on its feedforward and feedback paths. These drive enhancement elements, particularly in combination with the isolation element, may help to reduce the setup and hold times and enhance meta-stability resistance of the flip-flop relative to conventional implementations. Other embodiments are also disclosed.
摘要翻译： 一些实施例涉及具有数据输入端，数据输出端和时钟端的触发器。 触发器包括主锁存器，从锁存器和耦合在主锁存器输出和从锁存器之间的隔离元件。 隔离元件被布置成隔离来自从锁存器的主锁存器的输出所看到的电容性负载。 在一些实施例中，主锁存器在其前馈和反馈路径上包括一个或多个驱动增强元件。 从锁存器还可以在其前馈和反馈路径上包括一个或多个驱动增强元件。 这些驱动增强元件，特别是与隔离元件组合，可以有助于减小建立和保持时间，并且增强触发器相对于传统实现方式的元稳定性。 还公开了其他实施例。
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公开(公告)号：US20130113537A1
公开(公告)日：2013-05-09
申请号：US13292124
申请日：2011-11-09
申请人： Ming-Zhang KUO , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
发明人： Ming-Zhang KUO , Jen-Hang Yang , Shang-Chih Hsieh , Chih-Chiang Chang , Osamu Takahashi , Ta-Pen Guo , Sang Hoo Dong
CPC分类号： H03K3/033
摘要： A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
摘要翻译： 电路包括逻辑门和锁存器。 逻辑门被配置为在第一输入处接收时钟信号。 锁存器被布置在逻辑门的反馈回路中，并被配置为响应于由逻辑门输出的信号和时钟信号而将反馈信号输出到逻辑门的第二输入端。 电路被配置为基于时钟信号的上升沿或下降沿中的一个输出脉冲信号。
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公开(公告)号：US20130049810A1
公开(公告)日：2013-02-28
申请号：US13221628
申请日：2011-08-30
IPC分类号： H03D13/00
摘要： A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.
摘要翻译： 一个时间到当前的转换设备和方法。 提供具有用于选择性地接收时变周期信号或已知电压信号的输入的阻抗; 并且电流输出耦合到阻抗。 通过在一段时间内观察已知电压信号的阻抗的平均电流，并且通过观察时变周期信号的通过阻抗的平均电流，可以通过评估时变周期信号的占空比来确定时变周期信号的占空比 在电流输出处观察到的第一平均电流，而当所述已知电压信号耦合到所述阻抗时，所述时变周期信号与所述阻抗耦合到在所述电流输出处观察到的第二平均电流。 公开了一种实时的电流转换器电路。 提供了用于确定时变周期信号的占空比的方法实施例。
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公开(公告)号：US08253595B2
公开(公告)日：2012-08-28
申请号：US12648278
申请日：2009-12-28
申请人： Mu-Wen Yang , Chih-Chiang Chang
发明人： Mu-Wen Yang , Chih-Chiang Chang
摘要： A portable electronic device includes a main body, a housing and a protective cover. The main body includes a keypad. The housing is attached to the main body. The housing defines a receiving space and two guiding grooves. The two guiding grooves are positioned at two opposite sides of the receiving space and communicating with the receiving space. The protective cover includes two rails respectively engaged in the two guiding grooves. The protective cover is slidable in the receiving space along the guiding grooves to cover or expose the keypad.
摘要翻译： 便携式电子设备包括主体，壳体和保护盖。 主体包括一个小键盘。 外壳与主体相连。 壳体限定接收空间和两个引导槽。 两个引导槽位于接收空间的两个相对侧并且与接收空间连通。 保护盖包括分别接合在两个引导槽中的两个轨道。 保护盖沿着导槽在容纳空间中滑动以覆盖或暴露键盘。
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公开(公告)号：US08243425B2
公开(公告)日：2012-08-14
申请号：US12538279
申请日：2009-08-10
申请人： Mu-Wen Yang , Chih-Chiang Chang
发明人： Mu-Wen Yang , Chih-Chiang Chang
IPC分类号： H05K7/12
CPC分类号： H01H15/16 , H01H2003/466 , H01H2221/014 , H01H2221/044 , H01H2221/09 , H01H2229/044
摘要： A key assembly comprises a base plate, two resisting mechanisms and a key body. The resisting mechanisms and the key body are mounted the base plate, and the resisting mechanisms are respectively located at two opposite ends of the key body. When the key body slides toward and compresses one of the resisting mechanisms, said another one of the resisting mechanisms is stretched.
摘要翻译： 钥匙组件包括底板，两个阻力机构和钥匙体。 电阻机构和键体安装在基板上，电阻机构分别位于键体的两个相对端。 当键体滑动并压缩其中一个阻力机构时，所述另一个阻力机构被拉伸。
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