公开(公告)号：US09142630B2

公开(公告)日：2015-09-22

申请号：US13557479

申请日：2012-07-25

Applicant: Chang-Yu Wu ,  Chih-Chiang Chang ,  Shang-Chih Hsieh ,  Wei-Chih Hsieh

Inventor： Chang-Yu Wu ,  Chih-Chiang Chang ,  Shang-Chih Hsieh ,  Wei-Chih Hsieh

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4238 ,  H01L21/28123 ,  H01L29/78

Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.

Abstract translation: 除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。 在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。 与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。 因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它包括在该区域的非边缘内。 例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

公开(公告)号：US08667349B2

公开(公告)日：2014-03-04

申请号：US13207494

申请日：2011-08-11

Applicant: Shang-Chih Hsieh ,  Chih-Chiang Chang ,  Chang-Yu Wu

Inventor： Shang-Chih Hsieh ,  Chih-Chiang Chang ,  Chang-Yu Wu

IPC: G01R31/28

CPC classification number: G01R31/318541

Abstract: A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.

Abstract translation: 扫描触发器电路包括用于向数据节点提供数据信号的输入级，其中输入级包括耦合到数据节点的晶体管器件的第一和第二堆叠。 第一堆栈在用于输入到数据节点的正常操作模式期间接收数据输入信号，并且第二堆栈在用于输入到数据节点的扫描测试模式期间接收扫描输入信号。 扫描触发器电路还包括直接耦合到数据节点的主锁存器，用于锁存来自输入级的数据信号并输出​​数据信号; 耦合到主锁存器的输出的从锁存器，用于锁存来自主锁存器的输出并输出该输出; 以及扫描和时钟控制逻辑模块。 扫描和时钟控制逻辑模块控制第一个堆栈，以在正常操作模式下将数据输入信号输入到数据节点。

公开(公告)号：US20140027821A1

公开(公告)日：2014-01-30

申请号：US13557479

申请日：2012-07-25

Applicant: Chang-Yu Wu ,  Chih-Chiang Chang ,  Shang-Chih Hsieh ,  Wei-Chih Hsieh

Inventor： Chang-Yu Wu ,  Chih-Chiang Chang ,  Shang-Chih Hsieh ,  Wei-Chih Hsieh

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4238 ,  H01L21/28123 ,  H01L29/78

Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.

Abstract translation: 除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。 在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。 与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。 因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它被包括在该区域的非边缘内。 例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

公开(公告)号：US20120188794A1

公开(公告)日：2012-07-26

申请号：US13183007

申请日：2011-07-14

Applicant: Lon-Kou Chang ,  Chang-Yu Wu ,  Li-Wei Yen

Inventor： Lon-Kou Chang ,  Chang-Yu Wu ,  Li-Wei Yen

IPC: H02M3/335

CPC classification number: H02M3/33507 ,  H05B33/0809 ,  H05B33/0815 ,  H05B33/0845

Abstract: An adaptive bleeder circuit is applicable to a power converter, in which the power converter has a transformer primary side and a transformer secondary side, and the power converter enables input power to be selectively input or not input to the transformer primary side through a pulse-width-modulated signal. The adaptive bleeder circuit includes a switched bleeder circuit, and the bleeder circuit switch dynamically adjusts a turn on/off ratio (or referred to as duty ratio) of the switch element according to the TRIAC holding current and the converter input current of an alternating current (AC) TRIAC. When the input current is less than the holding current, the bleeder circuit increases conduction time ratio of the pulse-width-modulated signal, such that the input current recovers to the holding current to maintain normal conduction of the AC TRIAC.

Abstract translation: 自适应泄放电路适用于功率转换器，其中功率转换器具有变压器初级侧和变压器次级侧，并且功率转换器使得输入功率能够通过脉冲发生器选择性地输入或不输入到变压器初级侧， 宽度调制信号。 自适应泄放电路包括开关放电电路，泄放电路开关根据TRIAC保持电流和交流电流的转换器输入电流动态地调节开关元件的导通/截止比（或称为占空比） （AC）TRIAC。 当输入电流小于保持电流时，泄放电路增加了脉宽调制信号的导通时间比，使得输入电流恢复到保持电流以保持AC TRIAC的正常导通。

公开(公告)号：US20120033459A1

公开(公告)日：2012-02-09

申请号：US12970029

申请日：2010-12-16

Applicant: Lon Kou Chang ,  Chang Yu Wu ,  Hsing Fu Liu

Inventor： Lon Kou Chang ,  Chang Yu Wu ,  Hsing Fu Liu

IPC: H02M3/335

CPC classification number: H02M1/08 ,  H02M3/33523

Abstract: A circuit regulator is used to generate a pulse-width-modulation signal, so as to control a power to be selectively input or not input to a primary side of a switching power supply. The circuit regulator includes a synchronous timing pulse generation circuit, outputs a starting pulse after performing signal process of time delay, timing pulse regulation, and synchronization control on a pulse-width-modulation signal and a discharging time signal of a secondary side, and accordingly effectively controls a pulse starting time of the pulse-width-modulation signal. Therefore, the synchronous timing pulse generation circuit can be applied to the circuit regulator, so as to further effectively prevent an inductor current of the switching power supply from entering a Continuous Conduction Mode (CCM).

Abstract translation: 电路调节器用于产生脉冲宽度调制信号，以便控制有选择地输入或不输入到开关电源的初级侧的功率。 电路调节器包括同步定时脉冲发生电路，对次级侧的脉宽调制信号和放电时间信号进行时间延迟，定时脉冲调整，同步控制等信号处理后的起始脉冲输出 有效地控制脉冲宽度调制信号的脉冲开始时间。 因此，可以将同步定时脉冲发生电路应用于电路调节器，以进一步有效地防止开关电源的电感电流进入连续导通模式（CCM）。

公开(公告)号：US20160021715A1

公开(公告)日：2016-01-21

申请号：US14792909

申请日：2015-07-07

Applicant: Chang-Yu Wu ,  Wei-Ming Chiu

Inventor： Chang-Yu Wu ,  Wei-Ming Chiu

IPC: H05B33/08

CPC classification number: H05B33/0851 ,  H05B33/0815 ,  H05B33/0818

Abstract: The present invention provides a light emitting device driver circuit and a control circuit and a control method thereof. The light emitting device driver circuit is used for driving a light emitting device circuit according to a rectified dimming signal. The light emitting device driver circuit includes a power stage circuit and a control circuit. The control circuit includes a pulse width modulation (PWM) circuit, a current limit (CL) circuit, and a determination circuit. The CL circuit generates a CL signal according to a current sense signal and a predetermined CL threshold. The determination circuit is coupled to the PWM circuit and the CL circuit, for generating an operation signal according to a PWM signal and the CL signal. The power stage circuit maintains an absolute level of an AC dimming current not lower than a holding current in an ON phase period.

Abstract translation: 本发明提供一种发光装置驱动电路及其控制电路及其控制方法。 发光器件驱动电路用于根据整流调光信号驱动发光器件电路。 发光装置驱动电路包括功率级电路和控制电路。 控制电路包括脉冲宽度调制（PWM）电路，电流限制（CL）电路和确定电路。 CL电路根据电流检测信号和预定的CL阈值产生CL信号。 确定电路耦合到PWM电路和CL电路，用于根据PWM信号和CL信号产生操作信号。 功率级电路在ON阶段期间保持不低于保持电流的AC调光电流的绝对电平。

公开(公告)号：US20150340944A1

公开(公告)日：2015-11-26

申请号：US14706915

申请日：2015-05-07

Applicant: Tzu-Chen Lin ,  Chang-Yu Wu ,  Isaac Y. Chen

Inventor： Tzu-Chen Lin ,  Chang-Yu Wu ,  Isaac Y. Chen

IPC: H02M1/14 ,  H05B37/02

CPC classification number: H02M1/14 ,  H05B33/0815 ,  H05B33/0824 ,  H05B37/02

Abstract: The present invention discloses a light emitting device driver circuit, a current ripple rejecter therein, and a current ripple rejection method therefor. The light emitting device driver circuit includes: a power converter circuit, for converting an input voltage carrying an AC component to an output voltage and supplying an output current; and a current ripple rejecter, which is coupled to the power converter circuit, for filtering a ripple of the output current to generate a light emitting device current, and supplying the light emitting device current to a light emitting device circuit. The current ripple rejecter includes: a low-pass-filter circuit, for filtering the ripple of the output current to generate a filtered current; and a current amplification circuit, which is coupled to the low-pass-filter circuit, for amplifying the filtered current to generate an amplified current; wherein the light emitting device current includes the amplified current.

Abstract translation: 本发明公开了一种发光器件驱动电路，其中的电流纹波抑制器及其电流纹波抑制方法。 发光器件驱动电路包括：功率转换器电路，用于将承载AC分量的输入电压转换为输出电压并提供输出电流; 以及电流波纹抑制器，其耦合到功率转换器电路，用于滤波输出电流的纹波以产生发光器件电流，并将发光器件电流提供给发光器件电路。 电流纹波抑制器包括：低通滤波器电路，用于滤波输出电流的纹波以产生滤波电流; 以及电流放大电路，其耦合到所述低通滤波器电路，用于放大所述滤波电流以产生放大电流; 其中所述发光器件电流包括所述放大电流。

公开(公告)号：US08663970B1

公开(公告)日：2014-03-04

申请号：US13610015

申请日：2012-09-11

Applicant: Kuang-Tse Huang ,  Hau-Ren Chen ,  Wen-Chien Lee ,  Chang-Yu Wu ,  Hsin-Cheng Chen ,  Yu-Long Wu ,  Meng-Tsu Tsai ,  Ju-Ping Yeh ,  Yu-Wei Liang ,  Yu-Shiuan Lai

Inventor： Kuang-Tse Huang ,  Hau-Ren Chen ,  Wen-Chien Lee ,  Chang-Yu Wu ,  Hsin-Cheng Chen ,  Yu-Long Wu ,  Meng-Tsu Tsai ,  Ju-Ping Yeh ,  Yu-Wei Liang ,  Yu-Shiuan Lai

IPC: C12N1/00 ,  C12N15/74

CPC classification number: C12N15/81 ,  C07K14/395 ,  C12P7/06 ,  Y02E50/17

Abstract: The invention provides a yeast strain and a method for making the same. The method has the step of replacing the regulation region upstream of the hsp104 gene in the genome of the yeast, so as to accelerate and prolong the expression span of hsp104 gene and enhance the capability of the yeast to ferment and produce ethanol in a high-temperature environment. The yeast is capable of fermenting glucose at a temperature higher than 42° C. to produce ethanol, or biomass ethanol, wherein the ethanol production ratio based on fermentation of glucose is higher than 97%. Being able to synchronize the degradation/hydrolysis stage and fermentation stage of biomass ethanol producing process, the yeast in accordance with the present invention is able to lower the production cost of biomass ethanol and further raise the productivity with its high ethanol production ratio.

Abstract translation: 本发明提供酵母菌株及其制备方法。 该方法具有代替酵母基因组中hsp104基因上游调节区的步骤，加速并延长了hsp104基因的表达量，提高了酵母发酵和生产乙醇的能力， 温度环境。 酵母能够在高于42℃的温度下发酵葡萄糖以生产乙醇或生物质乙醇，其中基于葡萄糖发酵的乙醇生产比高于97％。 能够使生物质乙醇生产工艺的降解/水解阶段和发酵阶段同步，根据本发明的酵母能够降低生物质乙醇的生产成本，并且以高乙醇生产比进一步提高生产率。

公开(公告)号：US08610375B2

公开(公告)日：2013-12-17

申请号：US13183007

申请日：2011-07-14

Applicant: Lon-Kou Chang ,  Chang-Yu Wu ,  Li-Wei Yen

Inventor： Lon-Kou Chang ,  Chang-Yu Wu ,  Li-Wei Yen

IPC: H05B37/02

CPC classification number: H02M3/33507 ,  H05B33/0809 ,  H05B33/0815 ,  H05B33/0845

Abstract: An adaptive bleeder circuit is applicable to a power converter, in which the power converter has a transformer primary side and a transformer secondary side, and the power converter enables input power to be selectively input or not input to the transformer primary side through a pulse-width-modulated signal. The adaptive bleeder circuit includes a switched bleeder circuit, and the bleeder circuit switch dynamically adjusts a turn on/off ratio (or referred to as duty ratio) of the switch element according to the TRIAC holding current and the converter input current of an alternating current (AC) TRIAC. When the input current is less than the holding current, the bleeder circuit increases conduction time ratio of the pulse-width-modulated signal, such that the input current recovers to the holding current to maintain normal conduction of the AC TRIAC.

Abstract translation: 自适应泄放电路适用于功率转换器，其中功率转换器具有变压器初级侧和变压器次级侧，并且功率转换器使得输入功率能够通过脉冲发生器选择性地输入或不输入到变压器初级侧， 宽度调制信号。 自适应泄放电路包括开关放电电路，泄放电路开关根据TRIAC保持电流和交流电流的转换器输入电流动态地调节开关元件的导通/截止比（或称为占空比） （AC）TRIAC。 当输入电流小于保持电流时，泄放电路增加了脉宽调制信号的导通时间比，使得输入电流恢复到保持电流以保持AC TRIAC的正常导通。

公开(公告)号：US20130009616A1

公开(公告)日：2013-01-10

申请号：US13410034

申请日：2012-03-01

Applicant: Lon-Kou Chang ,  Hsing-Fu Liu ,  Chang-Yu Wu ,  Li-Wei Yen

Inventor： Lon-Kou Chang ,  Hsing-Fu Liu ,  Chang-Yu Wu ,  Li-Wei Yen

IPC: G05F1/455

CPC classification number: H05B33/0806 ,  H05B39/044 ,  Y02B20/348

Abstract: An auto-selecting holding current circuit is applicable to a converter. A primary side of the converter has a Triode for Alternating Current (TRIAC) and a bleeder circuit. The auto-selecting holding current circuit includes a first sensor module, a second sensor module and a reference voltage selecting circuit. The first sensor module detects an input current drop time or an input voltage drop time to output a sense signal. The second sensor module receives a current detector signal and outputs a critical current signal to detect a holding-current value range of the TRIAC. The reference voltage selecting circuit outputs a reference current signal to the bleeder circuit, and the reference current signal corresponds to a holding-current value of the TRIAC. Therefore, the bleeder circuit maintains normal operation of the TRIACs with different holding-current values.

Abstract translation: 自动选择保持电流电路适用于转换器。 转换器的初级侧具有交流电三极管（TRIAC）和泄放电路。 所述自动选择保持电流电路包括第一传感器模块，第二传感器模块和参考电压选择电路。 第一传感器模块检测输入电流下降时间或输入电压下降时间以输出感测信号。 第二传感器模块接收电流检测器信号并输出​​临界电流信号以检测TRIAC的保持电流值范围。 参考电压选择电路向放大器电路输出参考电流信号，并且参考电流信号对应于TRIAC的保持电流值。 因此，泄放电路保持具有不同保持电流值的TRIAC的正常工作。