公开(公告)号：USD605165S1

公开(公告)日：2009-12-01

申请号：US29337735

申请日：2009-05-28

申请人： Yaron Sheba ,  Philip L. Ly

设计人： Yaron Sheba ,  Philip L. Ly

公开(公告)号：US07616506B2

公开(公告)日：2009-11-10

申请号：US11617550

申请日：2006-12-28

申请人： Man Lung Mui ,  Seungpil Lee

发明人： Man Lung Mui ,  Seungpil Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418

摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.

摘要翻译： 由于基于相邻单元存储的电荷的电场耦合，可能会发生存储在非易失性存储单元中的诸如浮动栅极之类的电荷存储区域的视在电荷的变化。 为了解释这种偏差，在阅读时应用补偿。 当读取所选择的字线时，首先读取相邻的字线，并且将数据存储在每个位线的一组数据锁存器中。 每个位线的一个锁存器存储数据来自相邻字线的指示。 然后基于相邻字线上的单元格的不同状态，利用补偿来读取所选择的字线。 每个感测模块使用来自相邻字线的数据来选择感测结果，并对其位线进行适当的补偿。 来自相邻字线的数据在适当的时间用来自所选择的字线的数据被覆盖，并且指示被更新以反映锁存器存储来自所选字线的数据。 数据锁存器的有效使用消除了分离锁存器来存储来自相邻字线的数据的需要。

公开(公告)号：US07615447B2

公开(公告)日：2009-11-10

申请号：US11960498

申请日：2007-12-19

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。

公开(公告)号：US07606966B2

公开(公告)日：2009-10-20

申请号：US11530399

申请日：2006-09-08

申请人： Yan Li ,  Yupin Kawing Fong ,  Nima Mokhlesi

发明人： Yan Li ,  Yupin Kawing Fong ,  Nima Mokhlesi

IPC分类号： G06F13/10

CPC分类号： G11C7/1006 ,  G11C16/3418

摘要： Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.

摘要翻译： 易于实现的闪速存储器EEPROM内的随机化可以减少由于特定数据模式的重复和长期存储而导致的NAND串电阻效应，程序干扰，用户读取干扰以及浮动栅极与浮动栅极耦合。 在不同的实施例中，随机化可以是代码生成的伪随机化或用户驱动的随机化。 用户驱动的命令，其定时不能预测可用于触发和实现高水平的随机化。 随机改变数据的编码方案可防止特定数据模式的重复和长期存储。 即使用户希望长时间存储相同的信息，也可以重复存储，将以不同的编码方式进行随机编码，因此数据模式将会变化。

公开(公告)号：US07606091B2

公开(公告)日：2009-10-20

申请号：US11531217

申请日：2006-09-12

申请人： Yan Li ,  Loc Tu ,  Charles Moana Hook

发明人： Yan Li ,  Loc Tu ,  Charles Moana Hook

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/02 ,  G11C5/145 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/021 ,  G11C29/028

摘要： High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.

摘要翻译： 高性能非易失性存储器件具有为各种类型的存储器页和字线而修整的编程电压。 每个可擦除存储器块中的一组字线在连续的程序循环中进行测试，以最大限度地减少产生过多擦除/编程周期的问题。 对于给定类型的存储器页的最佳编程电压是从类似存储器页的样本的统计结果得出的。

公开(公告)号：US07606074B2

公开(公告)日：2009-10-20

申请号：US12242831

申请日：2008-09-30

申请人： Jun Wan ,  Jeffrey W Lutze ,  Chan-Sui Pang

发明人： Jun Wan ,  Jeffrey W Lutze ,  Chan-Sui Pang

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3468

摘要： Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.

摘要翻译： 在擦除操作期间，补偿电压施加到非易失性存储器系统以均衡存储器单元的擦除行为。 补偿电压可以补偿与其他存储器单元和/或选择栅极的NAND串的存储器单元电容耦合的电压。 补偿电压可以施加到一个或多个存储器单元，以基本上规范化存储器单元的擦除行为。 可以将补偿电压施加到NAND串的末端存储单元，以使其与NAND串的内部存储单元的擦除行为相等。 还可以将补偿电压施加到内部存储器单元，以使其与端部存储器单元的擦除行为相等。 此外，补偿电压可以施加到NAND串的一个或多个选择栅极，以补偿耦合到来自选择栅极的一个或多个存储器单元的电压。 可以使用各种补偿电压。

公开(公告)号：US07606071B2

公开(公告)日：2009-10-20

申请号：US11739501

申请日：2007-04-24

申请人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

发明人： Deepak Chandra Sekar ,  Nima Mokhlesi ,  Hao Thai Nguyen ,  Seungpil Lee ,  Man Lung Mui

IPC分类号： G11C16/06

CPC分类号： G11C8/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3436

摘要： A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

摘要翻译： 解决了在读取或验证操作期间由非易失性存储器件的源极线中的电压降引起的源极线偏置误差。 在一种方法中，通过将衬底耦合到源电压或作为源电压的函数的电压，将体偏置施加到非易失性存储器件的衬底。 在另一种方法中，控制栅极电压和/或漏极电压（例如位线电压）通过将其参考到基于源电压而不是接地的电压来补偿。 也可以使用这些方法的各种组合。 在其他操作中，例如编程，擦除验证和感测负阈值电压，源极偏置误差不存在，因此不需要偏置或补偿。 还可以补偿向前的身体偏差。

公开(公告)号：US07602652B2

公开(公告)日：2009-10-13

申请号：US12038421

申请日：2008-02-27

申请人： Teruhiko Kamei

发明人： Teruhiko Kamei

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/3418

摘要： Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may have greater effects in particular programming methodologies, and more specifically, when reading the neighboring cell for particular states or charge levels in those methodologies. In one embodiment, memory cells are programmed to create a wider margin between particular states where misreading a neighboring cell is more detrimental. Further, memory cells are read in one embodiment by compensating for floating gate coupling based on the state of a neighboring cell when reading at certain reference levels but not when reading at other reference levels, such as those where a wider margin has been created.

公开(公告)号：US07599241B2

公开(公告)日：2009-10-06

申请号：US11890734

申请日：2007-08-06

申请人： Steven T. Sprouse ,  Dhaval Parikh ,  Arjun Kapoor

发明人： Steven T. Sprouse ,  Dhaval Parikh ,  Arjun Kapoor

IPC分类号： G11C5/14

CPC分类号： G11C16/225

摘要： In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.

摘要翻译： 在具有由控制器控制的控制器和非易失性存储器阵列的非易失性存储器（NVM）器件中，电压监控器电路监视为NVM器件供电的电压源的输出。 电压监控器电路可以是NVM器件的一部分或耦合到其上。 电压监控器电路被配置为响应于检测到NVM器件供电的电压输出下降到预定值以下来断言“低电压”信号。 控制器被配置为在“低电压”信号被断言时将数据写入存储器阵列，并且在“低电压”信号被断言时暂停写入数据。 响应于“低电压”信号的声明，控制器完成写入周期/编程操作，如果挂起，并且在断言“低电压”信号期间防止任何额外的写周期/编程操作。

公开(公告)号：US07593265B2

公开(公告)日：2009-09-22

申请号：US11966325

申请日：2007-12-28

申请人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee

发明人： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee

IPC分类号： G11C16/26

CPC分类号： G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/26

摘要： In sensing a page of nonvolatile memory cells with a corresponding group of sense modules in parallel, as each high current cell is identified, it is locked out from further sensing while others in the page continued to be sensed. The sense module involved in the locked out is then in a lockout mode and becomes inactive. A noise source from the sense module becomes significant when in the lockout mode. The noise is liable to interfere with the sensing of neighboring cells by coupling through its bit line to neighboring ones. The noise can also couple through the common source line of the page to affect the accuracy of ongoing sensing of the cells in the page. Improved sense modules and method isolate the noise from the lockout sense module from affecting the other sense modules still active in sensing memory cell in the page.

摘要翻译： 在感测具有对应的一组感测模块的非易失性存储器单元的页面中，当识别出每个高电流单元时，它被锁定以进一步检测，而页面中的其他单元继续被感测。 被锁定的感测模块处于锁定模式并变为非活动状态。 当处于锁定模式时，来自感测模块的噪声源变得显着。 通过将其位线耦合到邻近单元，噪声容易干扰相邻单元的感测。 噪声也可以通过页面的公共源行耦合，以影响页面中单元格的持续感测的准确性。 改进的感测模块和方法将噪声与锁定感测模块隔离，以影响在页面中感测存储器单元中仍然有效的其他感测模块。