公开(公告)号：US09083578B1

公开(公告)日：2015-07-14

申请号：US13943047

申请日：2013-07-16

Applicant: Maxim Integrated Products, Inc.

Inventor： Jagdish Kumar Agrawal

IPC: H03L7/095 ,  H04L27/04 ,  H03L7/00 ,  G06F1/03

CPC classification number: G06F1/022 ,  G06F1/0328 ,  H03L7/095

Abstract: A numerically controlled oscillator (NCO) module includes a first accumulator circuit, a second accumulator circuit, and a phase-to-amplitude converter module. The first accumulator circuit receives a clock signal and at least first portions of each of multiple frequency control words and accumulates the first portions to generate a phase value. Each of the frequency control words identifies a fractional value and includes a respective one of the first portions and a respective second portion. The second accumulator circuit accumulates the second portions and generates a trigger signal based on a result of the accumulated second portions. The first accumulator circuit is configured to adjust the phase value based on the trigger signal. The phase-to-amplitude converter module generates a digital signal based on the clock signal and the phase value. An output transmits an output signal from the NCO module based on the digital signal.

Abstract translation: 数控振荡器（NCO）模块包括第一累加器电路，第二累加器电路和相位到幅度转换器模块。 第一累加器电路接收时钟信号和多个频率控制字中的每一个的至少第一部分，并且累积第一部分以产生相位值。 每个频率控制字识别分数值，并且包括第一部分中的相应一个和相应的第二部分。 第二累加器电路累积第二部分，并且基于累积的第二部分的结果产生触发信号。 第一累加器电路被配置为基于触发信号来调整相位值。 相到幅度转换器模块基于时钟信号和相位值产生数字信号。 输出基于数字信号从NCO模块发送输出信号。

公开(公告)号：US09065627B2

公开(公告)日：2015-06-23

申请号：US13873623

申请日：2013-04-30

Applicant: RPX Clearinghouse LLC

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC: H04L7/00 ,  G06F1/03 ,  H03L7/08 ,  H03L7/085 ,  H03L7/089 ,  H04J3/06

CPC classification number: H04L7/0079 ,  G06F1/0328 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/089 ,  H03L2207/50 ,  H04J3/0632 ,  H04J3/0658

Abstract: Transfer of differential timing over a packet network is provided. A transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract translation: 提供了通过分组网络传输差分定时。 发送业务接口接收业务时钟，并通过网络背板耦合到接收业务接口。 提供主参考时钟来对网络背板进行时间。 主参考时钟和服务时钟用于合成连接到发送服务接口的业务时钟的副本。 生成服务时钟和服务时钟的合成副本之间的误差的第一个控制字，并经由分组通过网络背板发送。 第一个控制字与主参考时钟一起用于重新创建用于定时接收服务接口的服务时钟。

公开(公告)号：US08467418B2

公开(公告)日：2013-06-18

申请号：US12268008

申请日：2008-11-10

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC: H04J3/06

CPC classification number: H04L7/0079 ,  G06F1/0328 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/089 ,  H03L2207/50 ,  H04J3/0632 ,  H04J3/0658

Abstract: A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract translation: 一种方法，系统和主服务接口通过分组网络传输差分定时。 发送业务接口接收业务时钟，通过网络背板耦合到接收业务接口。 提供主参考时钟来对网络背板进行时间。 主参考时钟和服务时钟用于合成连接到发送服务接口的业务时钟的副本。 生成服务时钟和服务时钟的合成副本之间的误差的第一个控制字，并经由分组通过网络背板发送。 第一个控制字与主参考时钟一起用于重新创建用于定时接收服务接口的服务时钟。

公开(公告)号：US08289095B1

公开(公告)日：2012-10-16

申请号：US13041145

申请日：2011-03-04

Applicant: Robert Mack ,  Timothy Jay Chen

Inventor： Robert Mack ,  Timothy Jay Chen

IPC: H03L1/00

CPC classification number: G06F1/022 ,  G06F1/0328 ,  G06F1/08 ,  H03B28/00 ,  H03B2200/0088 ,  H03L1/00 ,  H03L7/0994

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract translation: 一种用于通过改变用于增加NCO中的累加器的步长值来补偿NCO抖动以补偿不准确或不稳定的方法。 在一种方法中，可以监视累加器中的余数，并且可以产生接近理想时钟的当前边缘的补偿时钟。 在另一种方法中，在理想时钟的当前边缘被错过之后，可以产生靠近理想时钟的下一个边缘的补偿时钟。 步数值可以存储在可以是寄存器的存储器中。 抖动补偿器可以包括用于监视累加器中的余数的比较器或用于检测是否错过理想时钟的检测器。 抖动补偿器还可以将步长值改变为更快时钟的步进值以补偿抖动。

公开(公告)号：US20120259383A1

公开(公告)日：2012-10-11

申请号：US13081936

申请日：2011-04-07

Applicant: Stephen Trier ,  Jeffrey A. Weisgarber ,  Richard J. Polefko

Inventor： Stephen Trier ,  Jeffrey A. Weisgarber ,  Richard J. Polefko

IPC: A61N1/36

CPC classification number: A61N1/36146 ,  A61N1/36071 ,  A61N1/36125 ,  A61N1/3615 ,  A61N1/36167 ,  A61N1/36175 ,  A61N1/3625 ,  A61N1/37235 ,  G06F1/0328

Abstract: A method, device and/or system for generating arbitrary waveforms of a desired shape that can be used for generating a stimulation pulse for medical purposes such as for spinal cord stimulation therapy.

Abstract translation: 用于产生可用于产生用于医疗目的的刺激脉冲（例如脊髓刺激治疗）的期望形状的任意波形的方法，装置和/或系统。

公开(公告)号：US20110204935A1

公开(公告)日：2011-08-25

申请号：US12929857

申请日：2011-02-22

Applicant: Hiroki Kimura ,  Naoki Onishi ,  Shoichi Tsuchiya

Inventor： Hiroki Kimura ,  Naoki Onishi ,  Shoichi Tsuchiya

IPC: H03L7/099

CPC classification number: H03L7/08 ,  G06F1/0328

Abstract: Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.

Abstract translation: 提供一种在不降低噪声特性的同时抑制功耗的同时提高可靠性的PLL电路。 PLL电路包括将VCO的输出频率Fout分频的PLL IC，将相位与参考信号进行比较，并将相位差作为控制电压反馈到VCO。 控制电路能够精细地设定DDS电路中的参考频率Fref和输出频率Fdds，DDS电路基于频率的组合，生成用于Fref的Fdds和其整数倍频率的折叠信号。 第一AMP放大信号，可变滤波器选择所需的Fdd（所需），第二AMP放大信号并将其作为参考信号提供给PLL IC。 控制电路还向PLL IC提供分频比N.

公开(公告)号：US07898342B2

公开(公告)日：2011-03-01

申请号：US10980027

申请日：2004-11-03

Applicant: Boris Jasniewicz ,  Hartmut Keyl

Inventor： Boris Jasniewicz ,  Hartmut Keyl

IPC: H03L7/06

CPC classification number: H03L7/16 ,  G06F1/0328 ,  H03L7/0994

Abstract: In a circuit and a method of clock interpolation, an input signal at a first frequency is processed and at least one output signal having a second frequency being a multiple of the first frequency of the input signal is output. The circuit is defined by the fact that the input signal is measured with respect to frequency and phase in a PLL frequency measuring circuit, and by the fact that the measured input signal is multiplied by at least one frequency multiplier and an oscillator that follows the frequency multiplier.

Abstract translation: 在时钟插值的电路和方法中，处理第一频率的输入信号，并输出具有第二频率的输入信号的第一频率的倍数的至少一个输出信号。 该电路由以下事实定义：输入信号相对于PLL频率测量电路中的频率和相位被测量，并且由测量的输入信号乘以至少一个倍频器和跟随频率的振荡器 乘数。

公开(公告)号：US20110006811A1

公开(公告)日：2011-01-13

申请号：US12833113

申请日：2010-07-09

Applicant: Michael GERDING

Inventor： Michael GERDING

IPC: H03B21/00

CPC classification number: G06F1/0328 ,  H03B19/00 ,  H03B21/02

Abstract: A frequency synthesizer for a time base generator of a level measuring device which works according to the radar principle, with at least one first output for output of a first frequency signal, with at least one second output for output of a second frequency signal, and with a reference oscillator for producing a reference frequency signal, the first frequency signal and the second frequency signal having a small difference frequency relative to one another, the first frequency signal being producible by interaction of the reference oscillator with a direct digital synthesizer. The first frequency signal and second frequency signal can be generated with especially low noise by the second frequency signal being derived from the reference oscillator without interconnection of a direct digital synthesizer and the direct digital synthesizer being operated such that only a noise spectrum is produced which is at least partially minimized.

Abstract translation: 一种用于根据雷达原理工作的电平测量装置的时基发生器的频率合成器，具有用于输出第一频率信号的至少一个第一输出，以及用于输出第二频率信号的至少一个第二输出，以及 具有用于产生参考频率信号的参考振荡器，所述第一频率信号和所述第二频率信号相对于彼此具有小的差分频率，所述第一频率信号可通过所述参考振荡器与直接数字合成器的相互作用产生。 可以通过第二频率信号从参考振荡器得到第一频率信号和第二频率信号，而无需直接数字合成器和正在操作的直接数字合成器的互连，从而仅产生噪声谱 至少部分地最小化。

公开(公告)号：US07768355B2

公开(公告)日：2010-08-03

申请号：US11937362

申请日：2007-11-08

Applicant: Jeffery S. Patterson

Inventor： Jeffery S. Patterson

IPC: H03L7/085

CPC classification number: H03K5/156 ,  G06F1/0328 ,  H03K2005/00052

Abstract: A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.

Abstract translation: 公开了一种多相数控振荡器。 在相位累加器处接收输入信号。 相位累加器向相位内插器提供相位。 然后，相位插值器提供多个输出相位。 多个输出相位被提供给多个相位到幅度转换器。 所述多个相位幅度转换器中的每一个处理所述多个输出相位之一。

公开(公告)号：US20100079173A1

公开(公告)日：2010-04-01

申请号：US12039873

申请日：2008-02-29

Applicant: Stephen D. Larkin ,  Jeffrey H. Blake ,  Joseph F. Xavier ,  David E. Majchrzak

Inventor： Stephen D. Larkin ,  Jeffrey H. Blake ,  Joseph F. Xavier ,  David E. Majchrzak

IPC: H03B21/00

CPC classification number: G06F1/0328

Abstract: A method for controlling a synthesized local oscillator (SLO) includes: receiving a control input specifying a desired SLO output; receiving reference clock signal; generating a predefined set of dynamic clock signals from the reference clock signal; selecting a dynamic clock signal from the predefined set of dynamic clock signals in response to the control input; using the dynamic clock signal as an input to a direct digital synthesizer (DDS) module to generate a DDS output signal; selecting a DDS output band in response to the control input, the DDS output band including one of a baseband and an alias band; and processing the DDS output band to generate the SLO output.

Abstract translation: 一种用于控制合成本地振荡器（SLO）的方法包括：接收指定期望的SLO输出的控制输入; 接收参考时钟信号; 从所述参考时钟信号产生预定义的一组动态时钟信号; 响应于所述控制输入，从所述预定义的一组动态时钟信号中选择动态时钟信号; 使用动态时钟信号作为直接数字合成器（DDS）模块的输入，以产生DDS输出信号; 响应于控制输入选择DDS输出频带，DDS输出频带包括基带和别名频带之一; 并处理DDS输出频带以产生SLO输出。