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81.发明申请Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions 有权具有亚波长尺寸栅电极的半导体器件部分由直线形栅极电极形成的导电结构布局特征定义为具有最小端对端间隔和具有相应的非对称扩散区域的至少四个栅极电极轨迹公开(公告)号：US20100012982A1
公开(公告)日：2010-01-21
申请号：US12567555
申请日：2009-09-25
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication.
摘要翻译： 半导体器件包括：衬底部分，其具有限定在其中的多个扩散区域，相对于限定为将基底部分平分的虚拟线，以非对称的方式。 该半导体器件包括包含多个导电特征的栅极电平区域，该导电特征被限定为只在第一平行方向上延伸。 在第一并行方向上共享公共线的相邻导电特征的相邻的导电特征由相应的起始布局特征制成，所述相应起始布局特征由端对端间隔分开，所述端对端间隔的尺寸在栅极电极水平区域上具有基本相等的尺寸，并且被最小化 在一定程度上由半导体器件制造能力所允许。 导电特征沿着沿着第一并行方向的至少四个不同的虚拟线程限定。 导电特征的宽度小于用于其制造的光刻工艺中使用的光的波长。
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82.发明申请Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors 有权具有限制布局区域的半导体器件布局包括具有最小端到端间距和至少八个晶体管的线性形栅极电极布局特征公开(公告)号：US20100011333A1
公开(公告)日：2010-01-14
申请号：US12563077
申请日：2009-09-18
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a substrate portion of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight.
摘要翻译： 限制布局区域包括扩散级布局，其包括要在半导体器件的衬底部分内形成的多个扩散区域布局形状。 扩散区域布局形状限定至少一个p型扩散区域和至少一个n型扩散区域。 栅电极层布局被限定在衬底部分上方，以包括仅在第一平行方向上延伸的线性布局特征。 在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由 半导体器件制造能力。 半导体器件的限制布局区域中的PMOS晶体管器件和NMOS晶体管器件的总数大于或等于8。
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83.发明申请Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions 有权具有限制布局区域的半导体器件布局包括线性形栅极电极布局特征沿着至少四个栅极电极轨迹定义，具有最小端对端间隔和相应的非对称扩散区域公开(公告)号：US20100011330A1
公开(公告)日：2010-01-14
申请号：US12563063
申请日：2009-09-18
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction.
摘要翻译： 公开了半导体器件的布局中的限制布局区域，以包括包括多个扩散区域布局形状的扩散级布局。 多个扩散区域布局形状相对于被定义为将扩散级布局平分的中心线以非对称的方式定义。 栅极电极层布局被定义为包括仅在第一平行方向上延伸的线性布局特征。 在第一并行方向上共享共同的范围的相邻线性布局特征通过栅电极级布局基本上相等的端到端间隔相互分开，并且被最小化到由 半导体器件制造能力。 栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。
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84.发明申请Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions 有权半导体器件布局包括具有限制门极电极布局的电池布局，具有矩形形状的栅极电极布局特征定义为具有相应的非对称扩散区域的至少四个栅极电极轨迹公开(公告)号：US20100006986A1
公开(公告)日：2010-01-14
申请号：US12561216
申请日：2009-09-16
IPC分类号： H01L23/528 , H01L23/52
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout of the restricted layout region. The plurality of diffusion region layout shapes include a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. A gate electrode level layout is defined include a number of rectangular-shaped layout features placed to extend in only a first parallel direction, and defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.
摘要翻译： 限制布局区域被定义为包括扩散级布局，其包括要形成在半导体器件的衬底的一部分内的多个扩散区域布局形状。 多个扩散区域布局形状相对于限定为限制布局区域的扩散级别布局的二等分的中心线以非对称的方式定义。 多个扩散区域布局形状包括由中央非活性区域分隔的p型扩散区域布局形状和n型扩散区域布局形状。 栅极电极层布局被限定为多个矩形布置特征，其放置为仅在第一平行方向上延伸，并且沿第一平行方向上的至少四个不同的延伸线限定。 限制布局区域对应于单元布局的整个栅电极层。
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85.发明申请Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors 有权具有亚波长尺寸的栅极电极的半导体器件部分由矩形形状的栅极电极形成的布置特征并具有等量的PMOS和NMOS晶体管公开(公告)号：US20100006900A1
公开(公告)日：2010-01-14
申请号：US12563031
申请日：2009-09-18
IPC分类号： H01L27/105
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
摘要翻译： 半导体器件被公开为具有包括至少一个p型扩散区域和至少一个n型扩散区域的多个扩散区域的衬底部分。 栅极电极水平区域形成在衬底部分之上，以包括限定为仅沿第一平行方向延伸的多个导电特征。 栅极电平区域内的导电特征中的每一个由相应的起始矩形布局特征制成。 栅极电极区域内的导电特征中的每一个具有小于在光刻工艺中使用的光的波长的宽度以制造导电特征。 栅电极电平区域内的导电特征形成各自的PMOS晶体管器件和相应的NMOS晶体管器件。 多个PMOS晶体管器件等于栅电极电平区域中的NMOS晶体管器件的数量。
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86.发明申请Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors 有权具有限制布局区域的半导体器件布局包括矩形形栅极电极布局特性和等量的PMOS和NMOS晶体管公开(公告)号：US20100006897A1
公开(公告)日：2010-01-14
申请号：US12561220
申请日：2009-09-16
IPC分类号： H01L27/092 , H01L29/02
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device.
摘要翻译： 限制布局区域包括扩散级布局，其包括将在半导体器件的衬底的一部分内形成的多个扩散区布局形状。 扩散区域布局形状限定至少一个p型扩散区域和至少一个n型扩散区域。 限制布局区域包括定义为在衬底部分之上的栅电极层内图形导电特征的栅极电平布局。 栅极电极级布局包括放置为仅在第一平行方向上延伸的矩形布局特征。 一些矩形布局特征形成各个PMOS晶体管器件的栅电极，并且一些矩形布局特征形成各个NMOS晶体管器件的栅电极。 多个PMOS晶体管器件等于半导体器件的限制布局区域中的NMOS晶体管器件的数量。
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87.发明申请Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions 有权具有限制布局区域的半导体器件布局包括矩形形状的栅极电极布局特征定义为具有相应的非对称扩散区域的至少四个栅极电极轨迹公开(公告)号：US20100001321A1
公开(公告)日：2010-01-07
申请号：US12561207
申请日：2009-09-16
IPC分类号： H01L27/04 , H01L29/06 , H01L23/528
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. Each of a number of interconnect level layouts is defined to pattern conductive features within corresponding interconnect levels above the gate electrode level.
摘要翻译： 公开了半导体器件的布局中的限制布局区域，以包括包括多个扩散区域布局形状的扩散级布局。 多个扩散区域布局形状相对于被定义为将扩散级布局平分的中心线以非对称的方式定义。 栅极电极层布局被定义为包括放置为仅在第一平行方向上延伸的多个线性布局特征。 限制布局区域的栅极电平布局中的线形布局特征中的每一个都是矩形的。 栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。 多个互连电平布局中的每一个被定义为在栅电极电平以上的相应互连电平内对导电特征进行图案化。
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公开(公告)号：US20070210391A1
公开(公告)日：2007-09-13
申请号：US11683402
申请日：2007-03-07
IPC分类号： H01L29/76
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.
摘要翻译： 半导体器件包括衬底和限定在衬底内的多个扩散区域。 扩散区域通过衬底的非有源区域彼此分离。 半导体器件包括多个线性栅极电极轨道，其被限定为在单个共同方向上在衬底上延伸。 每个线性栅极电极轨道由一个或多个线性栅电极段限定。 限定在衬底的扩散区域和非有源区域上延伸的每个线性栅极电极轨迹，以使线性栅电极轨道内的相邻线性栅电极段的端部之间的间隔距离最小化，同时确保 相邻的线性栅电极段。
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公开(公告)号：US20240332305A1
公开(公告)日：2024-10-03
申请号：US18743961
申请日：2024-06-14
发明人： Sanghoon BAEK , Jungho DO , Jaewoo SEO , Jisu YU
IPC分类号： H01L27/118 , H01L23/48 , H01L27/02
CPC分类号： H01L27/11807 , H01L23/481 , H01L27/0207 , H01L2027/11829 , H01L2027/11864 , H01L2027/11881
摘要： A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.
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公开(公告)号：US12068326B2
公开(公告)日：2024-08-20
申请号：US18176463
申请日：2023-02-28
发明人： Young-Hun Kim , Jae-Seok Yang , Hae-Wang Lee
IPC分类号： H01L27/118 , H01L21/8238 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/823814 , H01L21/823878 , H01L27/0207 , H01L2027/11829 , H01L2027/11861 , H01L2027/11864 , H01L2027/11881
摘要： A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.
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