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    Interleaver for IEEE 802.11n standard
    82.
    发明申请
    Interleaver for IEEE 802.11n standard 有权
    IEEE 802.11n标准的交织器

    公开(公告)号：US20070140364A1

    公开(公告)日：2007-06-21

    申请号：US11313403

    申请日：2005-12-20

    申请人： Xuemei Ouyang ,  Chiu Ngo

    发明人： Xuemei Ouyang ,  Chiu Ngo

    IPC分类号： H04K1/10 ,  H04L27/00

    CPC分类号： H04L5/0046 ,  H03M13/2703 ,  H03M13/276 ,  H03M13/6527 ,  H04L1/0041 ,  H04L1/0059 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/04 ,  H04L1/06 ,  H04L5/0023

    摘要： A MIMO wireless system includes a transmitter having a parser that parses a bit stream into multiple spatial data streams and multiple interleavers corresponding to the multiple spatial data streams, where each interleaver interleaves the bits in the corresponding spatial data stream by performing frequency rotation after an interleaving operation, to increase diversity of the wireless system. The MIMO wireless system also includes a receiver that has deinterleavers that deinterleaves spatial bit streams transmitted by the transmitter.

    摘要翻译： MIMO无线系统包括具有将比特流解析为多个空间数据流的解析器的发射机和对应于多个空间数据流的多个交织器，其中每个交织器在交织之后执行频率旋转来交织相应空间数据流中的比特 操作，增加无线系统的多样性。 MIMO无线系统还包括具有解交织器的解交织器的接收机，其对由发射机发送的空间比特流进行解交织。

    Interleaving method and system
    85.
    发明申请
    Interleaving method and system 有权
    交错方式和系统

    公开(公告)号：US20070022262A1

    公开(公告)日：2007-01-25

    申请号：US11485449

    申请日：2006-07-13

    申请人： Jeong-sang Lee

    发明人： Jeong-sang Lee

    IPC分类号： G06F13/00

    CPC分类号： H03M13/276 ,  H03M13/2703

    摘要： An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are sequentially calculated according to a predetermined process, and reading data stored at read address values of the memory which are sequentially calculated according to a predetermined process, wherein the memory has N data banks, each data bank has M storage spaces, and there are D interleaving target data having data numbers A, and the storing data operation includes storing the data at storage spaces of the data banks, the storage spaces corresponding to integer values and the data banks corresponding to remainders obtained by dividing the data numbers A by results of dividing a total number of data D by the number of storage spaces M.

    摘要翻译： 采用符号交织，色调交织和用于发送数据的循环交织的交织方法包括以写入地址值存储数据，按照预定处理顺序计算的存储器中，以及顺序读取存储在存储器的地址值的数据 根据预定处理计算，其中存储器具有N个数据库，每个数据库具有M个存储空间，并且存在具有数据编号A的D个交织目标数据，并且存储数据操作包括将数据存储在数据的存储空间 存储空间对应于整数值的存储空间以及对应于通过将数据总数D除以存储空间数M的结果除以数据编号A而获得的余数的数据库。

    Method for iterative and non-iterative data detection using reduced-state soft-input/soft-output algorithms for complexity reduction
    86.
    发明授权
    Method for iterative and non-iterative data detection using reduced-state soft-input/soft-output algorithms for complexity reduction 有权

    公开(公告)号：US07096412B2

    公开(公告)日：2006-08-22

    申请号：US09882283

    申请日：2001-06-14

    申请人： Xiaopeng Chen ,  Keith M. Chugg

    发明人： Xiaopeng Chen ,  Keith M. Chugg

    IPC分类号： H03M13/03

    CPC分类号： H03M13/3746 ,  H03M13/256 ,  H03M13/2703 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3955 ,  H03M13/6331

    摘要： In a digital information processing system wherein a model of a finite state machine (FSM) receiving a plurality of FSM inputs and producing a plurality of FSM outputs is represented by a reduced-state trellis and wherein the FSM inputs are defined on a base closed set of symbols, a novel method is presented for updating soft decision information on the FSM inputs into higher confidence information whereby (1) the soft decision information is inputted in a first index set, (2) a forward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce forward state metrics, (3) a backward recursion is processed on the input soft decision information based on the reduced-state trellis representation to produce backward state metrics, wherein the backward recursion is independent of the forward recursion and (4) the forward state metrics and the backward state metrics are operated on to produce the higher confidence information.

    Interleaving/de-interleaving using compressed bit-mapping sequences
    87.
    发明申请
    Interleaving/de-interleaving using compressed bit-mapping sequences 有权

    公开(公告)号：US20060156094A1

    公开(公告)日：2006-07-13

    申请号：US11016643

    申请日：2004-12-17

    申请人： Dayong Chen

    发明人： Dayong Chen

    IPC分类号： G11C29/00

    CPC分类号： H03M13/6502 ,  H03M13/2703 ,  H03M13/2767

    摘要： A method of mapping input bit positions in an input sequence to output bit positions in an output sequence uses compressed mapping sequences stored in memory derived from a predetermined mapping function. The mapping function is decompressed into periodic component functions that are used to generate the compressed mapping sequences. Each compressed mapping sequence comprises a plurality of partial mapping values that represent one period of a corresponding component function or group of component functions. Partial mapping values are selected from each compressed mapping sequence based on a bit index of the current input bit and summed or otherwise combined to get an output index.

    Communication system method and apparatus
    88.
    发明授权
    Communication system method and apparatus 失效
    通信系统方法及装置

    公开(公告)号：US06975584B1

    公开(公告)日：2005-12-13

    申请号：US09676345

    申请日：2000-09-29

    申请人： Nikolai Schlegel ,  James Y. Hurt

    发明人： Nikolai Schlegel ,  James Y. Hurt

    IPC分类号： H03M13/27 ,  H04B1/69 ,  H04L1/00 ,  H04J11/00

    CPC分类号： H04L1/0071 ,  H03M13/2703 ,  H04L1/0041

    摘要： A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block (700) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

    摘要翻译： 提供一种用于在通信系统中有效处理信号的方法和装置。 用于发送的信号的处理可以包括以编码率1 / R编码数据块。 编码为数据块中的每个数据位产生R个数据符号。 一块RAM（299,600）被划分成多个RAM块，以允许同时从多个RAM块读取数据符号以同时产生同相和四相数据符号。 至少两个加扰器（306和307）用于同时加扰同相和四相数据符号。 沃尔什覆盖/求和块（700）紧随其后的加扰器提供了有效的沃尔什覆盖和信号来自通信系统的组合传输的信号。

    Method and apparatus for efficient Walsh covering and summing of signals in a communication system
    89.
    发明申请
    Method and apparatus for efficient Walsh covering and summing of signals in a communication system 有权
    用于在通信系统中有效Walsh覆盖和求和信号的方法和装置

    公开(公告)号：US20050201448A1

    公开(公告)日：2005-09-15

    申请号：US10959516

    申请日：2004-10-05

    申请人： Nikolai Schlegel ,  James Hurt

    发明人： Nikolai Schlegel ,  James Hurt

    IPC分类号： H03M13/27 ,  H04J11/00 ,  H04J13/00 ,  H04B1/707

    CPC分类号： H04J13/0048 ,  H03M13/2703

    摘要： A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block (700) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

    摘要翻译： 提供一种用于在通信系统中有效处理信号的方法和装置。 用于发送的信号的处理可以包括以编码率1 / R编码数据块。 编码为数据块中的每个数据位产生R个数据符号。 一块RAM（299,600）被划分成多个RAM块，以允许同时从多个RAM块读取数据符号以同时产生同相和四相数据符号。 至少两个加扰器（306和307）用于同时加扰同相和四相数据符号。 沃尔什覆盖/求和块（700）紧随其后的加扰器提供了有效的沃尔什覆盖和信号来自通信系统的组合传输的信号。

    Efficient multi-symbol deinterleaver
    90.
    发明申请
    Efficient multi-symbol deinterleaver 有权
    高效的多符号解交织器

    公开(公告)号：US20050190864A1

    公开(公告)日：2005-09-01

    申请号：US10789605

    申请日：2004-02-27

    申请人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    发明人： Hanfang Pan ,  Inyup Kang ,  James Krysl

    IPC分类号： H03M13/27 ,  H03M13/29 ,  H04L27/22 ,  H03D1/24

    CPC分类号： H03M13/2764 ,  H03M13/2703

    摘要： Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

    摘要翻译： 本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。 在一个方面，部署多个存储体以根据存储模式接收并同时存储多个值，诸如从调制星座确定的软判决值。 在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。 在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。 还提出了各种其他方面。 这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。