公开(公告)号：US06970386B2

公开(公告)日：2005-11-29

申请号：US10378414

申请日：2003-03-03

申请人： Shane C. Hollmer

发明人： Shane C. Hollmer

IPC分类号： G11C16/18 ,  G11C16/22 ,  G11C16/04

CPC分类号： G11C16/18 ,  G11C16/22

摘要： A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The security violation signal may optionally initiate a routine to clear sensitive data from memory or prevent the semiconductor circuit from further operation. The ultra-violet light detection circuit detects whether a semiconductor circuit has been exposed to ultra-violet light, for example, by employing a dedicated mini-array of non-volatile memory cells. At least two active bit lines, blprg and bler, are employed corresponding to program and erase, respectively. One of the bit lines is only programmable and the other bit line is only eraseable. Generally, all of the bits in the dedicated non-volatile memory array are initially in approximately the same state, which could be erased, programmed or somewhere in between. An offset current is added to one bit line and a change in the resulting current difference is used to detect an exposure to ultra-violet light.

摘要翻译： 公开了一种用于检测半导体电路是否已经暴露于紫外光的方法和装置。 紫外光检测电路检测到紫外光的曝光，并自动激活安全违规信号。 安全违规信号可以可选地启动例程以从存储器清除敏感数据或防止半导体电路进一步操作。 紫外光检测电路例如通过采用非易失性存储单元的专用微型阵列来检测半导体电路是否已经暴露于紫外光。 对应于编程和擦除分别使用至少两个有效位线blprg和bler。 其中一个位线只能编程，另一个位线只能擦除。 通常，专用非易失性存储器阵列中的所有位最初处于大致相同的状态，这可能被擦除，编程或其间的某处。 偏移电流被添加到一个位线，并且所得到的电流差的变化用于检测对紫外光的曝光。

公开(公告)号：US07071763B2

公开(公告)日：2006-07-04

申请号：US10378413

申请日：2003-03-03

申请人： Trevor Blyth

发明人： Trevor Blyth

IPC分类号： H03K17/687 ,  H03K17/08

CPC分类号： H03K17/122 ,  H03K17/102

摘要： A switching circuit is disclosed for switching high voltages and high currents, if necessary, without causing snapback or breakdown. The disclosed high voltage, high current switching circuit comprises a first set of series-connected transistors that includes a plurality of transistors to switch a high voltage without inducing snapback or breakdown; and a second set of series-connected transistors that includes one or more transistors to switch a high current. The first and second sets of series-connected transistors are connected in parallel. The gates of the second set of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector is connected to an output of the first and second sets of series-connected transistors. The output of the voltage detector is coupled to the enabling means.

摘要翻译： 公开了一种切换电路，用于在必要时切换高电压和高电流，而不会引起回跳或击穿。 所公开的高电压，大电流开关电路包括第一组串联连接的晶体管，其包括多个晶体管以切换高电压而不引起快速恢复或击穿; 以及第二组串联连接的晶体管，其包括用于切换高电流的一个或多个晶体管。 第一组和第二组串联晶体管并联连接。 第二组串联晶体管的栅极能够引起通过第二组串联晶体管的导通。 此外，电压检测器连接到第一和第二组串联晶体管的输出端。 电压检测器的输出耦合到启用装置。

公开(公告)号：US07032064B2

公开(公告)日：2006-04-18

申请号：US10376682

申请日：2003-02-28

申请人： Philip C. Barnett ,  David Sowards

发明人： Philip C. Barnett ,  David Sowards

IPC分类号： G06F12/00

CPC分类号： G11C16/30

摘要： A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

公开(公告)号：US06950336B2

公开(公告)日：2005-09-27

申请号：US10340342

申请日：2003-01-10

申请人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

发明人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

IPC分类号： G11C16/04 ,  G11C16/08

CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/08

摘要： An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).

摘要翻译： 公开了一种基于诸如闪存单元的非易失性浮动栅极存储器单元的模拟EEPROM存储器阵列，其中一小组位共享公共源极线和公共行线，使得该小组位可被视为 在编程和擦除模式下组合，以控制程序干扰和有效耐力的问题。 共享源线通用的位构成仿真EEPROM页面，它是可以擦除和重新编程的最小单元，而不会干扰其他位。 存储器阵列在物理上分成几组。 一个实施例采用四个存储器阵列，每个存储器阵列由32列和512页行组成（所有四个阵列提供总共1024页，每页具有8字节或64位）。 全局行解码器对主要行进行解码，并且页面行驱动程序和页面源驱动程序启用组成给定数组的各个行和源。 基于要访问的地址和访问模式（擦除，编程或读取），页面行驱动器和页面源驱动器由页面行/源供应解码器进行解码。

公开(公告)号：US07132873B2

公开(公告)日：2006-11-07

申请号：US10338551

申请日：2003-01-08

申请人： Shane C. Hollmer

发明人： Shane C. Hollmer

IPC分类号： H03K5/08

CPC分类号： H01L27/0266

摘要： An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot. The drain voltage of MXU0 will be at least one N-channel threshold, Vtn, lower than the input voltage level, nprot, and the drain voltage Vd of the bottom N-channel transistor, MXU1, is limited to less than the breakdown voltage, Vbreakdown.

摘要翻译： 公开了一种N沟道晶体管保护电路和方法，其防止在其漏极上具有高电压的N沟道晶体管中门控二极管击穿。 所公开的N沟道保护电路可以在高电压电平和较低电压电压之间的高电压模式下切换。 高电压转换电路通过将两个N沟道晶体管MXU0和MXU1之间的高电压分压来防止N沟道晶体管中的栅极二极管击穿，使得没有晶体管超过击穿电压，V < 。 中间电压驱动顶部的N沟道晶体管MXU 0。 顶部的N沟道晶体管MXU 0被门控，其电压电平至少为低于高电压电平V SUB的至少一个N沟道阈值V IN Tn ，使用中间电压电平，nprot。 MXU 0的漏极电压将至少比N输入电压电平NOUT和漏极电压V SUB小于N个通道阈值V SUB， 底部N沟道晶体管MXU 1被限制为小于击穿电压V分压。

公开(公告)号：US06988231B2

公开(公告)日：2006-01-17

申请号：US09809897

申请日：2001-03-16

申请人： Philip C. Barnett

发明人： Philip C. Barnett

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/2635 ,  G01R31/3187

摘要： A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).