公开(公告)号：US06400603B1

公开(公告)日：2002-06-04

申请号：US09564324

申请日：2000-05-03

申请人： Trevor Blyth ,  David Sowards ,  Dean Allum ,  Philip C. Barnett

发明人： Trevor Blyth ,  David Sowards ,  Dean Allum ,  Philip C. Barnett

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/0408 ,  G11C16/08

摘要： By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

摘要翻译： 通过减少在写入或擦除操作中必须擦除的FLASH EEPROM阵列中包含的块或页面的大小，减少所需寄存器的大小，使处理器更容易处理较小的信息块，减少 微处理器的尺寸和复杂性，并且增加了FLASH EEPROM的耐久性，从而允许其代替现有技术的EEPROM。 通过闪存EEPROM更换面罩ROM可以对代码存储区进行全面测试，并允许客户在其制造过程中使用该空间进行测试。 然后可以在最终装运前用最终代码存储来清除用于测试的代码并重新编程。

公开(公告)号：US5726934A

公开(公告)日：1998-03-10

申请号：US629729

申请日：1996-04-09

申请人： Hieu Van Tran ,  James Brennan, Jr. ,  Trevor Blyth ,  Sukyoon Yoon

发明人： Hieu Van Tran ,  James Brennan, Jr. ,  Trevor Blyth ,  Sukyoon Yoon

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  G11C29/00

CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/32 ,  G11C7/16

摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

摘要翻译： 本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。 这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，单元负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应 源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。 负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。 公开了该方法和替代实施例的细节。

公开(公告)号：US5164915A

公开(公告)日：1992-11-17

申请号：US644239

申请日：1991-01-22

申请人： Trevor Blyth

发明人： Trevor Blyth

IPC分类号： G10L13/04 ,  G11C7/16 ,  G11C11/56 ,  G11C27/00 ,  G11C27/02 ,  G11C27/04

CPC分类号： G11C7/16 ,  G11C11/5621 ,  G11C27/005 ,  G11C27/026 ,  G11C2207/16

摘要： Cascading analog record/playback devices allowing the recording and the playback duration of individual devices to be extended by connecting together multiple devices of the same type. Each such device contains both writing and reading circuits as well as memory circuits. The memory is embedded inside the device and does not have direct access to the outside of the device. All control functions relating to the selection of particular devices is done by the devices themselves without external intervention or assistance. A single input circuit and a single output circuit is used by all devices. In the case of a voice record and playback system, all devices use a single microphone and single loudspeaker.

摘要翻译： 通过将多个相同类型的设备连接在一起，可以扩展单个设备的记录和播放持续时间的级联模拟记录/播放设备。 每个这样的设备都包含写入和读取电路以及存储器电路。 内存嵌入设备内部，不能直接访问设备的外部。 与特定设备的选择相关的所有控制功能都由设备本身完成，无需外部干预或协助。 所有设备都使用单个输入电路和单个输出电路。 在语音记录和播放系统的情况下，所有设备都使用单个麦克风和单个扬声器。

公开(公告)号：US07071763B2

公开(公告)日：2006-07-04

申请号：US10378413

申请日：2003-03-03

申请人： Trevor Blyth

发明人： Trevor Blyth

IPC分类号： H03K17/687 ,  H03K17/08

CPC分类号： H03K17/122 ,  H03K17/102

摘要： A switching circuit is disclosed for switching high voltages and high currents, if necessary, without causing snapback or breakdown. The disclosed high voltage, high current switching circuit comprises a first set of series-connected transistors that includes a plurality of transistors to switch a high voltage without inducing snapback or breakdown; and a second set of series-connected transistors that includes one or more transistors to switch a high current. The first and second sets of series-connected transistors are connected in parallel. The gates of the second set of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector is connected to an output of the first and second sets of series-connected transistors. The output of the voltage detector is coupled to the enabling means.

摘要翻译： 公开了一种切换电路，用于在必要时切换高电压和高电流，而不会引起回跳或击穿。 所公开的高电压，大电流开关电路包括第一组串联连接的晶体管，其包括多个晶体管以切换高电压而不引起快速恢复或击穿; 以及第二组串联连接的晶体管，其包括用于切换高电流的一个或多个晶体管。 第一组和第二组串联晶体管并联连接。 第二组串联晶体管的栅极能够引起通过第二组串联晶体管的导通。 此外，电压检测器连接到第一和第二组串联晶体管的输出端。 电压检测器的输出耦合到启用装置。

公开(公告)号：US5808938A

公开(公告)日：1998-09-15

申请号：US887307

申请日：1997-07-02

申请人： Hieu Van Tran ,  James Brennan, Jr. ,  Trevor Blyth ,  Sukyoon Yoon

发明人： Hieu Van Tran ,  James Brennan, Jr. ,  Trevor Blyth ,  Sukyoon Yoon

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C27/00

CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/32 ,  G11C7/16

摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

摘要翻译： 本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。 这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应 源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。 负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。 公开了该方法和替代实施例的细节。

公开(公告)号：US5642316A

公开(公告)日：1997-06-24

申请号：US653073

申请日：1996-05-21

申请人： Hieu Van Tran ,  Trevor Blyth

发明人： Hieu Van Tran ,  Trevor Blyth

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/08 ,  G11C27/00 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C29/76 ,  G11C16/0441 ,  G11C16/08 ,  G11C29/789 ,  G11C29/80 ,  G11C29/812

摘要： A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.

摘要翻译： 用于非易失性存储芯片中的冗余电路，以增加由于制造缺陷导致的产量。 冗余电路包括冗余预解码器电路，源跟随器EEPROM（电可擦除可编程只读存储器）存储器熔丝，使用列高电压驱动器（也称为页锁存器）来编程EEPROM保险丝的方案，使用方案 作为冗余行解码器的常规行解码器（也称为字线驱动器或x解码器），以及作为冗余使能/禁止信号的外部绑定地址。

公开(公告)号：US5623436A

公开(公告)日：1997-04-22

申请号：US334589

申请日：1994-11-04

申请人： David Sowards ,  Trevor Blyth ,  Sakhawat Khan ,  Lawrence Engh

发明人： David Sowards ,  Trevor Blyth ,  Sakhawat Khan ,  Lawrence Engh

IPC分类号： G11C27/00

CPC分类号： G11C27/005

摘要： Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques for later playback. The invention allows setting of various parameters for the multi iterative programming technique after chip fabrication so as to allow tighter control and thus higher resolution analog signal sample storage in a given or minimum amount of time. Such parameters include, but are not limited to: the step down voltage from the coarse programming cycle to the fine programming cycle, the incremental voltage increase between each fine pulse, the pulse width of each fine pulse, the number of fine pulses, the incremental voltage increase between each coarse pulse, the pulse width of each course pulse, the number of coarse pulses, and the offset, VOS, which stops further coarse pulses and holds the last coarse level as a reference for the following fine cycle.

摘要翻译： 用于调整和控制利用片上修剪技术记录模拟信号的迭代方法以用于稍后播放的方法和装置。 本发明允许在芯片制造之后设置用于多重编程技术的各种参数，以允许在给定或最短时间内更严格的控制和因此更高分辨率的模拟信号样本存储。 这些参数包括但不限于：从粗编程周期到精细编程周期的降压电压，每个精细脉冲之间的增量电压增加，每个精细脉冲的脉冲宽度，精细脉冲数，增量 每个粗略脉冲之间的电压增加，每个脉冲的脉冲宽度，粗略脉冲的数量和偏移VOS，其停止进一步的粗略脉冲并保持最后的粗略电平作为以下精细周期的参考。

公开(公告)号：US06950336B2

公开(公告)日：2005-09-27

申请号：US10340342

申请日：2003-01-10

申请人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

发明人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

IPC分类号： G11C16/04 ,  G11C16/08

CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/08

摘要： An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).

摘要翻译： 公开了一种基于诸如闪存单元的非易失性浮动栅极存储器单元的模拟EEPROM存储器阵列，其中一小组位共享公共源极线和公共行线，使得该小组位可被视为 在编程和擦除模式下组合，以控制程序干扰和有效耐力的问题。 共享源线通用的位构成仿真EEPROM页面，它是可以擦除和重新编程的最小单元，而不会干扰其他位。 存储器阵列在物理上分成几组。 一个实施例采用四个存储器阵列，每个存储器阵列由32列和512页行组成（所有四个阵列提供总共1024页，每页具有8字节或64位）。 全局行解码器对主要行进行解码，并且页面行驱动程序和页面源驱动程序启用组成给定数组的各个行和源。 基于要访问的地址和访问模式（擦除，编程或读取），页面行驱动器和页面源驱动器由页面行/源供应解码器进行解码。

公开(公告)号：US06466488B2

公开(公告)日：2002-10-15

申请号：US09802184

申请日：2001-03-08

申请人： David Sowards ,  Trevor Blyth

发明人： David Sowards ,  Trevor Blyth

IPC分类号： G11C700

CPC分类号： G11C7/067 ,  G11C2207/063

摘要： A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.

摘要翻译： 逻辑电平检测电路，其包括读出放大器和与读出放大器拓扑不同的消耗平衡电路，并且通过具有依赖于数据的电消耗来减少和/或基本消除与数据相关的电消耗， 读出放大器。 感测放大器可以被实现为电流感测读出放大器，并且消耗平衡电路可以被实现为响应于由电流感测读出放大器产生的信号的有选择地使能的电流源。 与用于实现读出放大器的晶体管数量和芯片面积相比，消耗平衡电路可以用少量的晶体管和小的芯片面积实现。

公开(公告)号：US5969987A

公开(公告)日：1999-10-19

申请号：US243566

申请日：1999-02-03

申请人： Trevor Blyth ,  Richard T. Simko

发明人： Trevor Blyth ,  Richard T. Simko

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C27/005 ,  G11C7/16

摘要： Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state. A digital number can be represented by assigning a specific analog level to a digital number. The range of digital numbers that can be represented is determined by the analog voltage range divided by the accuracy to which the voltage may be stored and reliably retrieved. Other aspects and features of the invention are disclosed.