公开(公告)号：US06400603B1

公开(公告)日：2002-06-04

申请号：US09564324

申请日：2000-05-03

申请人： Trevor Blyth ,  David Sowards ,  Dean Allum ,  Philip C. Barnett

发明人： Trevor Blyth ,  David Sowards ,  Dean Allum ,  Philip C. Barnett

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/0408 ,  G11C16/08

摘要： By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

摘要翻译： 通过减少在写入或擦除操作中必须擦除的FLASH EEPROM阵列中包含的块或页面的大小，减少所需寄存器的大小，使处理器更容易处理较小的信息块，减少 微处理器的尺寸和复杂性，并且增加了FLASH EEPROM的耐久性，从而允许其代替现有技术的EEPROM。 通过闪存EEPROM更换面罩ROM可以对代码存储区进行全面测试，并允许客户在其制造过程中使用该空间进行测试。 然后可以在最终装运前用最终代码存储来清除用于测试的代码并重新编程。

公开(公告)号：US06510081B2

公开(公告)日：2003-01-21

申请号：US10022314

申请日：2001-12-18

申请人： Trevor Blyth ,  David Sowards ,  Philip C. Barnett

发明人： Trevor Blyth ,  David Sowards ,  Philip C. Barnett

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/0408 ,  G11C16/08

摘要： By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

公开(公告)号：US07032064B2

公开(公告)日：2006-04-18

申请号：US10376682

申请日：2003-02-28

申请人： Philip C. Barnett ,  David Sowards

发明人： Philip C. Barnett ,  David Sowards

IPC分类号： G06F12/00

CPC分类号： G11C16/30

摘要： A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

公开(公告)号：US5623436A

公开(公告)日：1997-04-22

申请号：US334589

申请日：1994-11-04

申请人： David Sowards ,  Trevor Blyth ,  Sakhawat Khan ,  Lawrence Engh

发明人： David Sowards ,  Trevor Blyth ,  Sakhawat Khan ,  Lawrence Engh

IPC分类号： G11C27/00

CPC分类号： G11C27/005

摘要： Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques for later playback. The invention allows setting of various parameters for the multi iterative programming technique after chip fabrication so as to allow tighter control and thus higher resolution analog signal sample storage in a given or minimum amount of time. Such parameters include, but are not limited to: the step down voltage from the coarse programming cycle to the fine programming cycle, the incremental voltage increase between each fine pulse, the pulse width of each fine pulse, the number of fine pulses, the incremental voltage increase between each coarse pulse, the pulse width of each course pulse, the number of coarse pulses, and the offset, VOS, which stops further coarse pulses and holds the last coarse level as a reference for the following fine cycle.

摘要翻译： 用于调整和控制利用片上修剪技术记录模拟信号的迭代方法以用于稍后播放的方法和装置。 本发明允许在芯片制造之后设置用于多重编程技术的各种参数，以允许在给定或最短时间内更严格的控制和因此更高分辨率的模拟信号样本存储。 这些参数包括但不限于：从粗编程周期到精细编程周期的降压电压，每个精细脉冲之间的增量电压增加，每个精细脉冲的脉冲宽度，精细脉冲数，增量 每个粗略脉冲之间的电压增加，每个脉冲的脉冲宽度，粗略脉冲的数量和偏移VOS，其停止进一步的粗略脉冲并保持最后的粗略电平作为以下精细周期的参考。

公开(公告)号：US5859803A

公开(公告)日：1999-01-12

申请号：US925020

申请日：1997-09-08

申请人： Hagop Nazarian ,  David Sowards ,  Lawrence D. Engh ,  Jung Sheng Hoei ,  May Lee

发明人： Hagop Nazarian ,  David Sowards ,  Lawrence D. Engh ,  Jung Sheng Hoei ,  May Lee

IPC分类号： G11C29/52 ,  G11C7/00 ,  H01L21/00

CPC分类号： G11C29/52

摘要： The present invention discloses a circuit for controlling operation of a functional circuit in a device based on a test result during testing. The circuit comprises a first storage element configured to be in one of a first state and a second state according to the test result, and a first sensing element coupled to the first storage element for generating a first signal used to control the operation of the functional circuit.

摘要翻译： 本发明公开了一种电路，用于根据测试中的测试结果控制设备中的功能电路的操作。 电路包括根据测试结果被配置为处于第一状态和第二状态之一的第一存储元件，以及耦合到第一存储元件的第一感测元件，用于产生用于控制功能的操作的第一信号 电路。

公开(公告)号：US06219291B1

公开(公告)日：2001-04-17

申请号：US09561710

申请日：2000-05-01

申请人： David Sowards ,  Trevor Blyth

发明人： David Sowards ,  Trevor Blyth

IPC分类号： G11C702

CPC分类号： G11C7/067 ,  G11C2207/063

摘要： A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.

摘要翻译： 逻辑电平检测电路，其包括读出放大器和与读出放大器拓扑不同的消耗平衡电路，并且通过具有依赖于数据的电消耗来减少和/或基本消除与数据相关的电消耗， 读出放大器。 感测放大器可以被实现为电流感测读出放大器，并且消耗平衡电路可以被实现为响应于由电流感测读出放大器产生的信号的有选择地使能的电流源。 与用于实现读出放大器的晶体管数量和芯片面积相比，消耗平衡电路可以用少量的晶体管和小的芯片面积实现。

公开(公告)号：US06950336B2

公开(公告)日：2005-09-27

申请号：US10340342

申请日：2003-01-10

申请人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

发明人： David Sowards ,  Trevor Blyth ,  Shane C. Hollmer

IPC分类号： G11C16/04 ,  G11C16/08

CPC分类号： G11C16/0408 ,  G11C16/0425 ,  G11C16/08

摘要： An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array. The page row drivers and page source drivers are decoded by a page row/source supply decoder, based on the addresses to be accessed and the access mode (erase, program or read).

摘要翻译： 公开了一种基于诸如闪存单元的非易失性浮动栅极存储器单元的模拟EEPROM存储器阵列，其中一小组位共享公共源极线和公共行线，使得该小组位可被视为 在编程和擦除模式下组合，以控制程序干扰和有效耐力的问题。 共享源线通用的位构成仿真EEPROM页面，它是可以擦除和重新编程的最小单元，而不会干扰其他位。 存储器阵列在物理上分成几组。 一个实施例采用四个存储器阵列，每个存储器阵列由32列和512页行组成（所有四个阵列提供总共1024页，每页具有8字节或64位）。 全局行解码器对主要行进行解码，并且页面行驱动程序和页面源驱动程序启用组成给定数组的各个行和源。 基于要访问的地址和访问模式（擦除，编程或读取），页面行驱动器和页面源驱动器由页面行/源供应解码器进行解码。

公开(公告)号：US06466488B2

公开(公告)日：2002-10-15

申请号：US09802184

申请日：2001-03-08

申请人： David Sowards ,  Trevor Blyth

发明人： David Sowards ,  Trevor Blyth

IPC分类号： G11C700

CPC分类号： G11C7/067 ,  G11C2207/063

摘要： A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.

摘要翻译： 逻辑电平检测电路，其包括读出放大器和与读出放大器拓扑不同的消耗平衡电路，并且通过具有依赖于数据的电消耗来减少和/或基本消除与数据相关的电消耗， 读出放大器。 感测放大器可以被实现为电流感测读出放大器，并且消耗平衡电路可以被实现为响应于由电流感测读出放大器产生的信号的有选择地使能的电流源。 与用于实现读出放大器的晶体管数量和芯片面积相比，消耗平衡电路可以用少量的晶体管和小的芯片面积实现。