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1.发明授权公开(公告)号：US11688770B2
公开(公告)日：2023-06-27
申请号：US17457161
申请日：2021-12-01
发明人： Praveen Shenoy
IPC分类号： H01L29/08 , H01L29/06 , H01L29/10 , H01L29/423 , H01L21/266
CPC分类号： H01L29/0847 , H01L29/0696 , H01L29/1033 , H01L29/42368 , H01L21/266
摘要： A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.
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公开(公告)号：US20230114503A1
公开(公告)日：2023-04-13
申请号：US17496805
申请日：2021-10-08
发明人： Keng Chen , Min Chen , James R. Garrett , Danny Clavette , Charles P. Amirault
IPC分类号： H02M3/158
摘要： A power supply includes a storage component to store an output current value representative of a magnitude of output current supplied by an output voltage of a power converter to power a load. The power supply further includes an offset reference generator and a controller. The offset reference generator produces an offset reference signal, the output current value being offset by the offset reference signal. The controller controls generation of the output voltage of the power converter as a function of the offset output current value with respect to a threshold signal (value). Additionally, the controller is configured to detect a startup mode of a power converter operative to convert an input voltage into an output voltage. During the startup mode, the controller: i) produces a threshold signal having a magnitude that varies over time, and ii) controls operation of switches in the power converter as a function of the threshold signal while the power converter is operated in a diode emulation mode. Implementation of the startup mode monotonically increases a magnitude of the output voltage without dips.
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公开(公告)号：US20210287952A1
公开(公告)日：2021-09-16
申请号：US16816823
申请日：2020-03-12
发明人： Shunhe Xiong
IPC分类号： H01L23/15 , H01L23/482 , H01L23/29 , H01L23/04 , H01L23/00
摘要： A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.
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公开(公告)号：US10707160B2
公开(公告)日：2020-07-07
申请号：US15817712
申请日：2017-11-20
发明人： Robert T. Carroll
IPC分类号： H01L23/498 , H01L23/495 , H01L23/00 , H01L21/48 , H01L21/768 , H01L23/482 , H01L23/50 , H01L27/06 , H01L29/423 , H02M3/335 , H01L27/088 , H02M3/158
摘要： According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
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公开(公告)号：US10666140B2
公开(公告)日：2020-05-26
申请号：US15243242
申请日：2016-08-22
发明人： Eung San Cho
摘要： In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.
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公开(公告)号：US10438876B2
公开(公告)日：2019-10-08
申请号：US15496951
申请日：2017-04-25
发明人： Dean Fernando , Roel Barbosa , Toshio Takahashi
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31
摘要： According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC.
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公开(公告)号：US20190124773A1
公开(公告)日：2019-04-25
申请号：US16224578
申请日：2018-12-18
发明人： Eung San Cho , Danny Clavette , Darryl Galipeau
IPC分类号： H05K3/00 , H05K1/11 , H05K3/32 , H05K3/40 , H05K3/46 , H05K1/18 , H05K1/14 , H01L23/00 , H01L23/538
摘要： In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
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公开(公告)号：US10205380B2
公开(公告)日：2019-02-12
申请号：US15431038
申请日：2017-02-13
发明人： Thomas J. Ribarich , Jorge Cerezo , Ajit Dubhashi
摘要： In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.
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公开(公告)号：US10199843B2
公开(公告)日：2019-02-05
申请号：US15015038
申请日：2016-02-03
发明人： Paul L. Schimel
IPC分类号： H02J7/00
摘要： There are disclosed herein various implementations of a connect/disconnect module for use with a battery pack. The connect/disconnect module includes a charge/discharge current path including multiple transistors having a first safe operating area (SOA), and a pre-charge current path coupled across the charge/discharge current path. The pre-charge current path includes multiple transistors having a second SOA that is significantly greater than the first SOA.
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公开(公告)号：US10141415B2
公开(公告)日：2018-11-27
申请号：US14993292
申请日：2016-01-12
发明人： Adam Amali , Ling Ma
IPC分类号： H01L29/423 , H01L21/027 , H01L29/417 , H01L29/66 , H01L29/739 , H01L29/78
摘要： A semiconductor device includes a gate trench in a semiconductor substrate, a source trench in the semiconductor substrate, the source trench having a first portion and a second portion under the first portion, where the first portion of the source trench is wider than the gate trench, and extends to a depth of the gate trench. The semiconductor device also includes a gate electrode and a gate trench dielectric liner in the gate trench, and a conductive filler and a source trench dielectric liner in the source trench. The semiconductor device further includes a source region between the gate trench and the source trench, a base region between the gate trench and the source trench, and a source contact coupled to the source region and the base region.
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