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公开(公告)号：US20210303490A1
公开(公告)日：2021-09-30
申请号：US17343704
申请日：2021-06-09
发明人： YUEH-CHUAN LU , CHING-HSIANG CHANG
摘要： An integrated circuit in a transmitter includes a multilane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively, (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier,
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公开(公告)号：US20210004030A1
公开(公告)日：2021-01-07
申请号：US16921842
申请日：2020-07-06
摘要： A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
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公开(公告)号：US10692568B2
公开(公告)日：2020-06-23
申请号：US16130807
申请日：2018-09-13
发明人： Shyh-Chyi Yang , Wei-Chiang Shih
IPC分类号： G11C11/419 , G11C7/10 , G11C11/412 , G11C11/413
摘要： A memory device includes: at least one memory cell; a bit line connected to the at least one memory cell; a write controller; a write driver receiving a logic signal from an output terminal of the write controller, and driving the bit line based on the logic signal; a negative voltage generator generating a reference voltage for receipt by a ground terminal of the write driver; and a protector connected to one of a power terminal and the output terminal of the write controller. The protector is capable of releasing stress voltage of the write driver.
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公开(公告)号：US10263715B1
公开(公告)日：2019-04-16
申请号：US15896071
申请日：2018-02-14
发明人： Shuo-Ting Kao
摘要： A post-cursor compensation system includes a state detector that receives a signal on a data line to detect a predefined state, and accordingly generates a clear control signal; a synchronization detector that receives the signal on the data line and the clear control signal to detect at least one synchronization state, and accordingly generates a trigger signal; and a compensation generator that receives the trigger signal and accordingly generates a compensation signal.
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公开(公告)号：US09455725B2
公开(公告)日：2016-09-27
申请号：US14860711
申请日：2015-09-22
CPC分类号： H03L7/081 , H03K5/01 , H03K2005/00286 , H03L7/0807 , H03L7/091 , H03L7/095 , H03L7/1075 , H03L7/113
摘要： A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.
摘要翻译： 相位检测器包括多个采样电路，逻辑电路，多个解复用器和判定电路，其中多个采样电路使用具有不同相位的多个时钟信号来分别采样数据信号以产生多个采样 结果; 所述逻辑电路根据所述多个采样结果产生N个相位超前信号和N个相位滞后信号; 多个解复用器分别对N个相位超前信号和N个相位延迟信号执行解复用操作，分别产生M相前导输出信号和M相位滞后输出信号; 并且判决电路根据M相前导输出信号和M相位滞后输出信号产生最终相位超前信号和最终相位滞后信号。
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6.发明授权公开(公告)号：US09100264B2
公开(公告)日：2015-08-04
申请号：US14465847
申请日：2014-08-22
发明人： Ting-Chun Huang , Kuan-Yu Chen
CPC分类号： H04L25/4902 , H04B1/06
摘要： The present invention provides a digital receiver configured to demodulate or decode a pulse-width modulated (PWM) signal from a transmitter. The receiver digitally demodulates or decodes the pulse-width modulated signal so as to obtain (binary) values of data modulated on pulse periods of the pulse-width modulated signal. The digital receiver includes multiple delay cells coupled to one another in series and a sampling circuit coupled to one of the delay cells. A sequential coupling of the delay cells composes a signal path, and each of the delay cells is designed to provide a corresponding delay to a corresponding input signal propagating along the signal path so as to generate a delayed signal as its output.
摘要翻译： 本发明提供了一种数字接收机，被配置为对来自发射机的脉宽调制（PWM）信号进行解调或解码。 接收机对脉冲宽度调制信号进行数字解调或解码，以获得在脉冲宽度调制信号的脉冲周期上调制的数据的（二进制）值。 数字接收机包括串联耦合的多个延迟单元和耦合到延迟单元之一的采样电路。 延迟单元的顺序耦合构成信号路径，并且每个延迟单元被设计为向沿着信号路径传播的相应输入信号提供相应的延迟，以便产生延迟信号作为其输出。
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公开(公告)号：US20210313998A1
公开(公告)日：2021-10-07
申请号：US17223933
申请日：2021-04-06
发明人： HUI HUAN WANG , MENG HSUAN WU
摘要： A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.
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公开(公告)号：US10886882B2
公开(公告)日：2021-01-05
申请号：US16264928
申请日：2019-02-01
发明人： Ching-Hsiang Chang
摘要： A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.
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公开(公告)号：US10692567B2
公开(公告)日：2020-06-23
申请号：US16123459
申请日：2018-09-06
发明人： Zhi-Xian Chou , Wei-Chiang Shih
IPC分类号： G11C11/419 , G11C8/08 , G11C7/12
摘要： A method for assisting a memory cell in an access operation is provided. The method includes: setting a supply voltage to a first supply voltage level to determine a reference probability value of the memory cell applied by the first supply voltage level; applying an assist voltage to an access line coupled to the memory cell, and setting the supply voltage to a second supply voltage level to determine a relationship between the assist voltage and the access failure probability of the memory cell applied by the second supply voltage level; determining, from the relationship, a target assist voltage level of the assist voltage corresponding to the reference probability value; and providing an assist circuit configured to apply the target assist voltage level to the access line during the access operation, wherein the memory cell is applied by the second supply voltage level during the access operation.
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公开(公告)号：US10686454B2
公开(公告)日：2020-06-16
申请号：US16268625
申请日：2019-02-06
发明人： Ming-Ting Wu
摘要： A clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pump unit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, the current-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.
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