公开(公告)号：US06914908B1

公开(公告)日：2005-07-05

申请号：US09420129

申请日：1999-10-19

申请人： Michel Harrand ,  Claire Henry

发明人： Michel Henry

IPC分类号： G06F15/16 ,  G06F13/12 ,  G06F13/16 ,  G06F15/177 ,  G06T1/20 ,  H04N7/26 ,  H04J3/02

CPC分类号： G06F13/1605 ,  G06F13/126

摘要： The invention relates to a multitask processing system including a data bus and a command bus. Each one of a plurality of operators is provided to perform a processing determined by an instruction and is likely to issue a command request in order to receive an instruction from the command bus and to issue a transfer request on response to an acknowledgment of the command request, in order to receive or provide data being processed, through the data bus. A memory controller arbitrates the transfer requests and manages the data transfers on the data bus between the operators and a memory. A sequencer arbitrates the command requests, determines instructions to provide the operators with, and manages the instruction transfer through the command bus.

摘要翻译： 本发明涉及包括数据总线和命令总线的多任务处理系统。 提供多个运算符中的每一个以执行由指令确定的处理，并且可能发出命令请求以便从命令总线接收指令并且响应于命令请求的确认发出转移请求 ，以便通过数据总线接收或提供正在处理的数据。 存储器控制器仲裁传送请求并管理数据总线上的操作员和存储器之间的数据传输。 定序器仲裁命令请求，确定提供操作者的指令，并通过命令总线管理指令传输。

公开(公告)号：US6163790A

公开(公告)日：2000-12-19

申请号：US101615

申请日：1998-07-09

申请人： Guy Monier

发明人： Guy Monier

IPC分类号： G06F7/52 ,  G06F7/72 ,  G09C1/00 ,  G06F7/38

CPC分类号： G06F7/728 ,  G06F7/535 ,  G06F2207/5353

摘要： A modular arithmetic coprocessor designed to perform computations according to the Montgomery method includes a division circuit to perform integer divisions. The integer division circuit computes the division of a binary data element A encoded on n+n (bits by a binary data element B encoded on n bits, A, B, n, n' and n" being on-zero integers. For this function, the integer division circuit includes: a first n-bit register and a second n-bit register to contain the binary data element A and the result of the division, a third n-bit register to contain an intermediate result, a fourth n-bit register to contain the binary data element B, two subtraction circuits each having a first series input and a second series input and a series output, and a test circuit having an input and an output.

摘要翻译： PCT No.PCT / FR97 / 00035 Sec。 371日期：1998年7月9日 102（e）日期1998年7月9日PCT 1997年1月9日PCT PCT。 公开号WO97 / 25668 日期1997年7月17日设计用于根据蒙哥马利方法执行计算的模数算术协处理器包括执行整数除法的分频电路。 整数分割电路计算在n + Z + n上编码的二进制数据元素A的分割（由n位编码的二进制数据元素B的比特，A，B，n，n'和n“为零整数 对于该功能，整数分割电路包括：第一n位寄存器和第二n位寄存器，用于包含二进制数据元素A和除法运算结果，第三n位寄存器包含中间结果， 包含二进制数据元素B的第四n位寄存器，具有第一串联输入和第二串联输入和串联输出的两个减法电路，以及具有输入和输出的测试电路。

公开(公告)号：US6156594A

公开(公告)日：2000-12-05

申请号：US970070

申请日：1997-11-13

申请人： Yvon Gris

发明人： Yvon Gris

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L27/0635

摘要： The present invention relates to a method for fabricating an integrated circuit including MOS transistors and a bipolar transistor of NPN type, including the steps of: forming the MOS transistors, covering the entire structure with a protection layer, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon, a second layer of silicon nitride and a second oxide layer, opening these last three layers at the center of the emitter-base region of the bipolar transistor, and depositing a third silicon nitride layer, forming spacers, removing the apparent parts of the third layer of silicon nitride, and depositing a third N-type doped polysilicon layer.

摘要翻译： 本发明涉及一种用于制造包括MOS晶体管和NPN型双极晶体管的集成电路的方法，包括以下步骤：形成MOS晶体管，用保护层覆盖整个结构，在基极处打开保护层， 双极晶体管的发射极位置，形成多晶硅的第一P型掺杂层，第二氮化硅层和第二氧化物层，在双极晶体管的发射极 - 基极区域的中心处打开最后三层，以及 沉积第三氮化硅层，形成间隔物，去除第三层氮化硅的表观部分，以及沉积第三N型掺杂多晶硅层。

公开(公告)号：US6147521A

公开(公告)日：2000-11-14

申请号：US876282

申请日：1997-06-12

申请人： Hubert Degoirat ,  Mathieu Lisart

发明人： Hubert Degoirat ,  Mathieu Lisart

IPC分类号： G01R19/165 ,  H03K5/153 ,  H03K3/037

CPC分类号： G01R19/1659 ,  G01R19/16519

摘要： The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

公开(公告)号：US6143059A

公开(公告)日：2000-11-07

申请号：US157737

申请日：1998-09-21

申请人： Abdallah Tangi ,  Mohamed Elhark ,  Ali Ben Bachir ,  Abdallah Shriri ,  Mohamed Cherkaoui ,  Mohamed Ebntouhami ,  Mustapha Saaoudi El

发明人： Abdallah Tangi ,  Mohamed Elhark ,  Ali Ben Bachir ,  Abdallah Shriri ,  Mohamed Cherkaoui ,  Mohamed Ebntouhami ,  Mustapha Saaoudi El

IPC分类号： C23C18/36 ,  H05K3/24

CPC分类号： C23C18/36 ,  H05K3/244

摘要： Disclosed are a self-catalytic bath and a method for the deposition of Ni-P alloy on a substrate. The bath comprises nickel sulfate, sodium hypophosphite as a reducing agent, acetic acid as a buffer and traces of lead as a stabilizer. It also includes a citrate used as a complexing agent associated with a gluconate used both as a catalyst and a stabilizer. The disclosed bath makes it possible to tolerate large quantities of hypophosphite and is relatively long-lived. Furthermore, it can be used to prepare large quantities of Ni-P alloy per liter of solution.

摘要翻译： 公开了一种自催化浴和用于在基底上沉积Ni-P合金的方法。 该浴包括硫酸镍，次磷酸钠作为还原剂，乙酸作为缓冲剂和痕量铅作为稳定剂。 它还包括用作与用作催化剂和稳定剂的葡萄糖酸盐相关联的络合剂的柠檬酸盐。 所公开的浴使得可以耐受大量的次磷酸盐并且相对长寿。 此外，它可以用于每升溶液制备大量的Ni-P合金。

公开(公告)号：USRE36934E

公开(公告)日：2000-10-31

申请号：US10957

申请日：1993-01-29

申请人： Thierry Arnaud

发明人： Thierry Arnaud

IPC分类号： H04M9/08 ,  H04M1/60

CPC分类号： H04M9/08

摘要： A control device for a hands-free telephone set automatically controls microphone and amplifier gains so that a feedback loop has less than unity gain to avoid circuit instability and resultant self-oscillation. An emission channel includes a microphone, a signal compressor and a controllable attenuator. A reception channel includes a signal compressor, an adjustable attenuator and a loudspeaker. The combination of the emission and reception channels form an amplification loop whereby the output of the reception channel is acoustically coupled to the input of the emission channel while the output of the emission channel is coupled to the input of the reception channel through a common telephone line. To avoid circuit oscillation, a circuit initially sets the gain of the loop to a predetermined value slightly less than unity (0 db) and subsequently maintains the loop gain constant by maintaining the sum of the compressor and attenuator gains at a fixed value.

摘要翻译： 用于免提电话机的控制装置自动控制麦克风和放大器增益，使得反馈回路具有小于单位增益以避免电路不稳定性和由此产生的自振荡。 发射通道包括麦克风，信号压缩器和可控衰减器。 接收通道包括信号压缩器，可调衰减器和扬声器。 发射和接收信道的组合形成一个放大环路，其中接收信道的输出与发射信道的输入声学耦合，而发射信道的输出通过公共电话线耦合到接收信道的输入端 。 为了避免电路振荡，电路首先将环路的增益设置为略小于一（0db）的预定值，然后通过将压缩器和衰减器增益之和保持在固定值来维持环路增益恒定。

公开(公告)号：US6130460A

公开(公告)日：2000-10-10

申请号：US93302

申请日：1998-06-08

申请人： Joseph Borel

发明人： Joseph Borel

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L23/52 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L21/4763

CPC分类号： H01L27/0251 ,  H01L2924/0002 ,  Y10S438/91

摘要： An interconnect track connects, on several metallization levels, an insulated gate of a transistor to a discharge diode within an integrated circuit. The interconnect track comprises a first track element extending under the highest metallization level, having a first end connected to the gate and having a length greater than a predetermined critical length. This first track element includes an interrupted track portion at a site a first distance less than the critical length away from the first end. This point is compatible with the placement of the metallization level above, and extends between two insulating layers on the same metallization level. The two branches of the interrupted portion are mutually connected by a metallic filling contact which also extends in the insulating support layer of the metallization level immediately above that containing the interrupted track portion.

摘要翻译： 互连轨道在几个金属化层面上连接晶体管的绝缘栅极到集成电路内的放电二极管。 互连轨道包括在最高金属化水平下延伸的第一轨道元件，其具有连接到栅极并具有大于预定临界长度的长度的第一端。 该第一轨道元件包括在距离第一端的临界长度小于第一距离的位置处的中断的轨道部分。 这一点与上述金属化水平的放置兼容，并且在相同的金属化水平上在两个绝缘层之间延伸。 中断部分的两个分支通过金属填充接触相互连接，金属填充接触件也在刚好包含中断的轨道部分的金属化水平的绝缘支撑层中延伸。

公开(公告)号：US6108232A

公开(公告)日：2000-08-22

申请号：US32630

申请日：1998-02-27

申请人： Brigitte Hennebois ,  Jean-Yves Monari, deceased ,  by Serge Monari ,  Claudine Monari, heirs ,  by Philippe Monari, heir

发明人： Brigitte Hennebois ,  Jean-Yves Monari, deceased ,  by Serge Monari ,  Claudine Monari, heirs ,  by Philippe Monari, heir

IPC分类号： G11C7/10 ,  G11C11/419 ,  G11C11/00

CPC分类号： G11C11/419 ,  G11C7/1015 ,  G11C7/1048

摘要： In a static RAM, a complete erasure of the memory is achieved by sequentially propagating an erasure control signal from one group of memory cells to a next group of memory cells through delay circuits calibrated to correspond to a maximum time duration of erasure of the previous group of cells.

摘要翻译： 在静态RAM中，通过将擦除控制信号从一组存储器单元传送到下一组存储器单元，通过经过校准以对应于先前组的擦除的最大持续时间的延迟电路来实现存储器的完全擦除 的细胞。

公开(公告)号：US6081396A

公开(公告)日：2000-06-27

申请号：US966043

申请日：1997-11-07

申请人： Marc Henri Ryat

发明人： Marc Henri Ryat

IPC分类号： G01R31/02 ,  G01R31/00 ,  G11B5/02 ,  G11B5/455 ,  G11B19/04 ,  G11B5/09

CPC分类号： G11B19/04 ,  G11B5/02

摘要： A read/write head for a magnetic medium magnetic is modified by the addition to it of a parallel-connected resistor and by the measurement of the difference in voltage at the terminals of this unit, on the one hand when the read/write head and the resistor are perfectly connected and, on the other hand, when one of the connections is in an open circuit condition or even in short-circuit condition with respect to ground. Consequently, a measurement is taken, preferably, of the state of connection of the read/write head when it is in read mode and not when it is in write mode. It is shown that far greater reliability in the detection of this type of defect is obtained, in avoiding false alarms.

摘要翻译： 一个磁性介质磁盘的读/写头通过并联电阻器的补充以及本机端子上的电压差的测量来改变，一方面当读/写头和 电阻器是完美连接的，另一方面，当其中一个连接处于开路状态或甚至相对于地面处于短路状态时。 因此，优选地，读取/写入头处于读取模式而不是处于写入模式时的连接状态进行测量。 可以看出，在这种缺陷的检测中获得了更大的可靠性，以避免误报。

公开(公告)号：US6067657A

公开(公告)日：2000-05-23

申请号：US108060

申请日：1998-06-30

申请人： Sylvie Wuidart

发明人： Sylvie Wuidart

IPC分类号： G06F12/16 ,  G06F11/00 ,  G06F11/36

CPC分类号： G06F11/3648

摘要： A detection circuit for a microcontroller includes a decoding circuit to decode the addressing codes of the memory to detect an addressing of the cell. The detection circuit also includes a circuit for decoding the instruction codes to detect the instructions comprising an access to the cell, and a logic circuit to give an alarm signal when an addressing of the cell is done in the absence of an instruction including an access to the cell.

摘要翻译： 用于微控制器的检测电路包括解码电路，用于对存储器的寻址码进行解码以检测单元的寻址。 检测电路还包括用于对指令代码进行解码以检测包括对单元的访问的指令的电路，以及逻辑电路，当在没有指令的情况下完成小区的寻址时给出报警信号，该指令包括访问 细胞。