公开(公告)号：US09692336B2

公开(公告)日：2017-06-27

申请号：US14880008

申请日：2015-10-09

Applicant: Texas Instruments Incorporated

Inventor： David Patrick Magee ,  Jorge Zambada

IPC: H02P6/16 ,  H02P21/00 ,  H02P21/14

CPC classification number: H02P21/0003 ,  H02P21/14 ,  H02P21/18 ,  H02P21/24

Abstract: A motor controller architecture and method of operating the same. The motor controller asynchronously generates multiphase control signals for a multi-phase electric motor, relative to the estimation of various state parameters used in generating those control signals. Latency between the state estimation task and the control signal generation task is addressed by storing a timestamp with each input data sample from the sensors, and maintaining that timestamp with the output data from state estimation. Knowledge of the timestamp value allows the control task to update the state estimates to compensate for the time difference between the input data sample and the current sampling period.

公开(公告)号：US08898528B2

公开(公告)日：2014-11-25

申请号：US13887862

申请日：2013-05-06

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/3185 ,  G11C29/48

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318544 ,  G01R31/318547 ,  G11C29/48

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract translation: 一种过程和装置提供一种JTAG TAP控制器（302），以使用减少的引脚数，高速DDR接口（202）来访问设备的JTAG TAP域（106）。 通过将来自TAP控制器的单独TDI和TMS信号组合成单个信号并在驱动DDR接口的TCK的上升沿和下降沿传送单个信号的TDI和TMS信号来实现接入。 TAP域可以以点对点方式或以可寻址总线方式耦合到TAP控制器。 对TAP域的访问可用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

公开(公告)号：US20110158407A1

公开(公告)日：2011-06-30

申请号：US13043119

申请日：2011-03-08

Applicant: Erdal Paksoy ,  Narendar Shankar ,  Sven-Inge Redin

Inventor： Erdal Paksoy ,  Narendar Shankar ,  Sven-Inge Redin

IPC: H04K1/00 ,  H04L9/30

CPC classification number: G06F21/60 ,  G06F21/35 ,  G06F21/78 ,  G06F2221/2105 ,  H04W12/02 ,  H04W12/06 ,  H04W88/02

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space. Other processes of manufacture, processes of operation, circuits, devices, wireless and wireline communications products, wireless handsets and systems are disclosed and claimed.

Abstract translation: 电子电路包括具有用于存储数据的基于硬件的安全性的更安全的处理器。 较不安全的处理器最终利用数据。 通过在更安全的处理器和较不安全的处理器之间的数据传输请求 - 响应布置，更安全的处理器赋予较不安全的处理器上的数据更大的安全性。 制造过程使得具有存储空间的手持设备，用于执行调制解调器软件的较不安全的处理器以及具有受保护应用和安全存储的更安全的处理器。 制造过程涉及产生每设备私钥和公开密钥对，将私钥存储在安全存储器中，在该存储器中可以被受保护的应用程序访问，将公开密钥与调制解调器软件组合以产生组合的软件， 组合软件; 并将签名的组合软件存储到存储空间中。 公开并要求保护其他制造工艺，操作过程，电路，设备，无线和有线通信产品，无线手机和系统。

公开(公告)号：US20070279126A1

公开(公告)日：2007-12-06

申请号：US11422509

申请日：2006-06-06

Applicant: Jagadeesh Krishnan ,  Srinath M. Ramaswamy ,  Gangadhar Burra

Inventor： Jagadeesh Krishnan ,  Srinath M. Ramaswamy ,  Gangadhar Burra

IPC: H03F3/38

CPC classification number: H03F3/2173 ,  H03F1/34 ,  H03F2200/351

Abstract: A closed loop amplifier adapted to be directly connected to a battery having a battery voltage for powering the amplifier. The amplifier includes an amplifier stage having a node for receiving a control voltage for controlling a common mode voltage of the stage, a digital voltage indicator for generating a digital value corresponding to the battery voltage, and a common mode voltage supply providing the control voltage corresponding to the digital value.In a preferred embodiment, a Class-D amplifier is powered by a power supply providing power by way of a power supply voltage node and a ground node, the amplifier having improved common-mode voltage control. A first integrator stage receives an input signal and provides an output signal, the integrator stage having a first common-mode reference voltage applied thereto for control of the common-mode voltage of the integrator stage. A second integrator stage receives an input signal and provides an output signal, the integrator stage having a second common-mode reference voltage applied thereto for control of the common-mode voltage of the integrator stage. A comparator stage receives the output of the first integrator stage and the output of the second integrator stage and provides an output signal corresponding to the difference between them. An output stage provides an output of the amplifier. A digital voltage indicator generates a digital value corresponding to the voltage at the power supply voltage node, while a common-mode voltage supply provides the first common-mode reference voltage corresponding to the digital value.

Abstract translation: 适于直接连接到具有用于为放大器供电的电池电压的电池的闭环放大器。 放大器包括放大器级，具有用于接收用于控制级的共模电压的控制电压的节点，用于产生对应于电池电压的数字值的数字电压指示器，以及提供相应的控制电压的共模电压电源 到数字值。 在优选实施例中，D类放大器由通过电源电压节点和接地节点提供功率的电源供电，该放大器具有改进的共模电压控制。 第一积分器级接收输入信号并提供输出信号，积分器级具有施加到其上的第一共模参考电压以用于控制积分器级的共模电压。 第二积分器级接收输入信号并提供输出信号，积分器级具有施加到其上的第二共模参考电压，用于控制积分器级的共模电压。 比较器级接收第一积分器级的输出和第二积分器级的输出，并提供对应于它们之间的差的输出信号。 输出级提供放大器的输出。 数字电压指示器产生对应于电源电压节点处的电压的数字值，而共模电压电源提供对应于数字值的第一共模参考电压。

公开(公告)号：US07158684B2

公开(公告)日：2007-01-02

申请号：US10364104

申请日：2003-02-11

Applicant: Ngai-Man Cheung ,  Yuji Itoh

Inventor： Ngai-Man Cheung ,  Yuji Itoh

IPC: G06K9/36

CPC classification number: H04N19/136 ,  H04N19/13 ,  H04N19/139 ,  H04N19/172 ,  H04N19/61

Abstract: A method of variable length coding classifies each received symbol into one of a plurality of classifications having a corresponding variable length code table selected based upon a probability distribution of received symbols within the classification. The variable length codeword output corresponds to the received symbol according to the variable length code table corresponding to the classification of that received symbol. The plurality of classifications and the corresponding variable length code tables may be predetermined and fixed. Alternatively, the variable length code table may be dynamically determined with data transmitted from encoder to decoder specifying the variable length code tables and their configurations. Universal variable length code (UVLC) is used to code the symbols. Universal variable length code can instantiate to different variable length code tables with different parameters.

Abstract translation: 可变长度编码的方法将每个接收到的符号分类为具有基于分类内的接收符号的概率分布而选择的对应的可变长度码表的多个分类中的一个。 根据与该接收符号的分类对应的可变长度码表，可变长度码字输出对应于接收符号。 多个分类和对应的可变长度码表可以是预定和固定的。 或者，可变长度代码表可以用指定可变长度代码表及其配置的从编码器发送到解码器的数据来动态地确定。 通用可变长度代码（UVLC）用于对符号进行编码。 通用可变长度代码可以实例化为具有不同参数的不同可变长度代码表。

公开(公告)号：US06952750B2

公开(公告)日：2005-10-04

申请号：US09965143

申请日：2001-09-27

Applicant: Hugo Cheung ,  Lu Yuan ,  Terence Chiu

Inventor： Hugo Cheung ,  Lu Yuan ,  Terence Chiu

IPC: G06F1/32 ,  G06F13/00

CPC classification number: G06F1/3228 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a bus interface connected to one or more peripheral interface using logic processes to enable microcontroller-based products and other components and devices to achieve a low power data transmission between central processors and peripheral devices. In accordance with an exemplary embodiment, a low power embedded system bus architecture comprises logic devices, for example, an OR gate for passing through only data from a selected peripheral device. To facilitate the throughput of data, the non-selected peripheral devices may only provide logic zero to the OR gate. The logic device arrangement may comprise any combination of logic devices which performs the function of eliminating the need for tristate buffers. Through the elimination of tristate buffers, the present invention can lower the power consumed by the microcontroller, and improves the ability to test a large portion of the devices. In accordance with an exemplary embodiment, an AND gate is provided in each peripheral device for providing a logic zero when the peripheral device is not selected, and for providing data when the peripheral device is selected. In addition the AND gate eliminates the occurrence of high impedance Z states.

Abstract translation: 根据本发明的三无总线接口通信方案解决了现有技术的许多缺点。 根据本发明的各个方面，低功率嵌入式系统总线架构具有总线接口，该总线接口使用逻辑过程连接到一个或多个外围接口，以使基于微控制器的产品和其他组件和设备能够实现低功率数据 中央处理器和外围设备之间的传输。 根据示例性实施例，低功率嵌入式系统总线架构包括逻辑设备，例如，用于仅通过来自所选外围设备的数据的或门。 为了便于数据吞吐量，未选择的外围设备可能只向OR门提供逻辑0。 逻辑器件布置可以包括执行消除对三态缓冲器的需要的功能的逻辑器件的任何组合。 通过消除三态缓冲器，本发明可以降低微控制器消耗的功率，并且提高测试大部分设备的能力。 根据示例性实施例，在每个外围设备中提供与门，用于当未选择外围设备时提供逻辑0，并且在选择外围设备时提供数据。 此外，与门消除了高阻抗Z状态的发生。

公开(公告)号：US10580722B1

公开(公告)日：2020-03-03

申请号：US16134924

申请日：2018-09-18

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/62 ,  H01L29/00 ,  H01L23/552 ,  H01L23/544 ,  H01L23/495 ,  H01L23/532

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US20110162082A1

公开(公告)日：2011-06-30

申请号：US13043103

申请日：2011-03-08

Applicant: Erdal Paksoy ,  Narendar Shankar ,  Sven-Inge Redin

Inventor： Erdal Paksoy ,  Narendar Shankar ,  Sven-Inge Redin

IPC: G06F21/00

CPC classification number: G06F21/60 ,  G06F21/35 ,  G06F21/78 ,  G06F2221/2105 ,  H04W12/02 ,  H04W12/06 ,  H04W88/02

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space. Other processes of manufacture, processes of operation, circuits, devices, wireless and wireline communications products, wireless handsets and systems are disclosed and claimed.

Abstract translation: 电子电路包括具有用于存储数据的基于硬件的安全性的更安全的处理器。 较不安全的处理器最终利用数据。 通过在更安全的处理器和较不安全的处理器之间的数据传输请求 - 响应布置，更安全的处理器赋予较不安全的处理器上的数据更大的安全性。 制造过程使得具有存储空间的手持设备，用于执行调制解调器软件的较不安全的处理器以及具有受保护应用和安全存储的更安全的处理器。 制造过程涉及产生每设备私钥和公开密钥对，将私钥存储在安全存储器中，在该存储器中可以被受保护的应用程序访问，将公开密钥与调制解调器软件组合以产生组合的软件， 组合软件; 并将签名的组合软件存储到存储空间中。 公开并要求保护其他制造工艺，操作过程，电路，设备，无线和有线通信产品，无线手机和系统。

公开(公告)号：US20110161650A1

公开(公告)日：2011-06-30

申请号：US13043150

申请日：2011-03-08

Applicant: Erdal Paksoy ,  Narendar Shankar ,  Sven-Inge Redin

Inventor： Erdal Paksoy ,  Narendar Shankar ,  Sven-Inge Redin

IPC: G06F21/00 ,  G06F9/24

CPC classification number: G06F21/60 ,  G06F21/35 ,  G06F21/78 ,  G06F2221/2105 ,  H04W12/02 ,  H04W12/06 ,  H04W88/02

Abstract: An electronic circuit includes a more-secure processor having hardware based security for storing data. A less-secure processor eventually utilizes the data. By a data transfer request-response arrangement between the more-secure processor and the less-secure processor, the more-secure processor confers greater security of the data on the less-secure processor. A manufacturing process makes a handheld device having a storage space, a less-secure processor for executing modem software and a more-secure processor having a protected application and a secure storage. A manufacturing process involves generating a per-device private key and public key pair, storing the private key in a secure storage where it can be accessed by the protected application, combining the public key with the modem software to produce a combined software, signing the combined software; and storing the signed combined software into the storage space. Other processes of manufacture, processes of operation, circuits, devices, wireless and wireline communications products, wireless handsets and systems are disclosed and claimed.

Abstract translation: 电子电路包括具有用于存储数据的基于硬件的安全性的更安全的处理器。 较不安全的处理器最终利用数据。 通过在更安全的处理器和较不安全的处理器之间的数据传输请求 - 响应布置，更安全的处理器赋予较不安全的处理器上的数据更大的安全性。 制造过程使得具有存储空间的手持设备，用于执行调制解调器软件的较不安全的处理器以及具有受保护应用和安全存储的更安全的处理器。 制造过程涉及产生每设备私钥和公开密钥对，将私钥存储在安全存储器中，在该存储器中可以被受保护的应用程序访问，将公开密钥与调制解调器软件组合以产生组合的软件， 组合软件; 并将签名的组合软件存储到存储空间中。 公开并要求保护其他制造工艺，操作过程，电路，设备，无线和有线通信产品，无线手机和系统。

公开(公告)号：US20100241724A1

公开(公告)日：2010-09-23

申请号：US12545359

申请日：2009-08-21

Applicant: Gary L. Swoboda

Inventor： Gary L. Swoboda

IPC: G06F15/16 ,  G06F19/00

CPC classification number: G06F11/0793

Abstract: This invention is a method of operating a system having multiple finite state machines and a controller controlling an operational state of each finite state machine. Upon selection by the controller of a changed operational state, each finite state machine determines if it supports the changed operational state. If the finite state machine supports the changed operational state, it enters the changed operational state. If the finite state machine does not support the changed operational state, it enters an offline state. The controller may also determine whether a changed operational state is supported by each finite state machine.

Abstract translation: 本发明是一种操作具有多个有限状态机的系统和控制每个有限状态机的操作状态的控制器的方法。 在由控制器选择改变的操作状态时，每个有限状态机确定其是否支持改变的操作状态。 如果有限状态机支持改变的操作状态，则进入改变的操作状态。 如果有限状态机不支持改变的操作状态，则它进入脱机状态。 控制器还可以确定每个有限状态机是否支持改变的操作状态。