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    Multilevel semiconductor device and structure
    1.
    发明授权
    Multilevel semiconductor device and structure 有权

    公开(公告)号：US11164898B2

    公开(公告)日：2021-11-02

    申请号：US17216597

    申请日：2021-03-29

    申请人： Monolithic 3D Inc.

    发明人： Zvi Or-Bach ,  Deepak C. Sekar

    IPC分类号： H01L27/146 ,  H01L33/16 ,  H01L25/075 ,  H01L27/15 ,  H01L33/62

    摘要： A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs), a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.

    3D semiconductor device and structure
    2.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US11145657B1

    公开(公告)日：2021-10-12

    申请号：US17367386

    申请日：2021-07-04

    申请人： Monolithic 3D Inc.

    发明人： Zvi Or-Bach ,  Brian Cronquist

    IPC分类号： H01L27/108 ,  G11C5/02 ,  H01L27/06 ,  H01L21/822

    摘要： A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer which includes second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes at least one scan-chain to support circuit test.

    3D memory device and structure
    6.
    发明授权
    3D memory device and structure 有权

    公开(公告)号：US11251149B2

    公开(公告)日：2022-02-15

    申请号：US17485504

    申请日：2021-09-27

    申请人： Monolithic 3D Inc.

    发明人： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC分类号： H01L21/46 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/544 ,  H01L25/00

    摘要： A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.

    Automation for monolithic 3D devices
    8.
    发明授权
    Automation for monolithic 3D devices 有权

    公开(公告)号：US11205034B2

    公开(公告)日：2021-12-21

    申请号：US17385082

    申请日：2021-07-26

    申请人： Monolithic 3D Inc.

    发明人： Zvi Or-Bach ,  Zeev Wurman

    IPC分类号： G06F30/392 ,  G06F30/394

    摘要： A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit controlling the first memory array, where the first placement includes placement of the first memory array, and the second placement includes placement of the first logic circuit based on the placement of the first memory array.

    Multilevel semiconductor device and structure with electromagnetic modulators
    10.
    发明授权
    Multilevel semiconductor device and structure with electromagnetic modulators 有权

    公开(公告)号：US11163112B2

    公开(公告)日：2021-11-02

    申请号：US17330186

    申请日：2021-05-25

    申请人： Monolithic 3D Inc.

    发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    IPC分类号： G02B6/12 ,  H01L27/146 ,  H01L27/15

    摘要： A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.