公开(公告)号：US5804814A

公开(公告)日：1998-09-08

申请号：US447208

申请日：1995-05-22

申请人： Toru Musha ,  Akihiko Yoshizawa ,  Hiroyuki Imabayashi ,  Hiroshi Miyajima

发明人： Toru Musha ,  Akihiko Yoshizawa ,  Hiroyuki Imabayashi ,  Hiroshi Miyajima

IPC分类号： G02B5/30 ,  G02B27/28 ,  G11B7/12 ,  G11B7/135 ,  G11B7/22 ,  G11B11/105 ,  G01J1/20

CPC分类号： G11B7/1356 ,  G02B27/283 ,  G02B5/3083 ,  G11B11/10543 ,  G11B7/123 ,  G11B7/22

摘要： An optical pick-up head for reading writing information from on a magneto-optical record medium including a semiconductor laser, a multi-image plane parallel plate for separating an incident light beam emitted by the semiconductor laser from a return light beam reflected by the optical record medium and dividing the return beam transmitted through and refracted by the multi-image plane parallel plate into a plurality of return light beams, and a signal detecting photodetector receiving a plurality of return light beams, wherein the multi-image plane parallel plate is formed by first and second prisms made of birefringent material and is arranged such that major and minor axes of astigmatism introduced by the plane parallel plate are inclined by 45.degree. with respect to an information track. An optic axis of the first prism is set such that the return beam is separated into ordinary and extraordinary light beams having identical intensities and an optic axis of the second prism is rotated with respect to the optic axis of the first prism. The optical elements are positioned and mounted on a mounting substrate having guide walls formed by a photolithography.

公开(公告)号：US4792227A

公开(公告)日：1988-12-20

申请号：US21286

申请日：1987-03-03

申请人： Akihiko Yoshizawa

发明人： Akihiko Yoshizawa

IPC分类号： G01N21/21 ,  G01M11/00 ,  G01N21/23 ,  G01N21/41 ,  G11B7/26 ,  G11B11/105

CPC分类号： G01N21/23 ,  G11B11/10582 ,  G11B7/26

摘要： An apparatus (31) and method for measuring the refractive index of an optical recording medium substrate (34) wherein an angle of incidence of a polarized beam (33) is set at an oblique angle of incidence with the substrate (34), the polarized direction of the polarized beam (33) is varied for the substrate (34) in this state, the transmitted or reflected light beam by the substrate is received by a light receiving means (36) through a light analyzer means (35) in the crossed Nichol state and the received light amount for the polarized angle is measured and is compared with a theoretical formula so that the refractive index in the thickness direction of the substrate can be measured.

摘要翻译： 一种用于测量光记录介质衬底（34）的折射率的装置（31）和方法，其中偏振光束（33）的入射角被设置为与衬底（34）成倾斜的入射角，偏振 在该状态下，偏振光束（33）的方向对于基板（34）而变化，基板的透射或反射光束被光接收装置（36）通过穿过的光分析器装置（35）接收 测量Nichol状态和接收到的偏振角的光量，并与理论公式进行比较，从而可以测量基板厚度方向的折射率。

公开(公告)号：US06538490B2

公开(公告)日：2003-03-25

申请号：US10097307

申请日：2002-03-15

申请人： Akihiko Yoshizawa

发明人： Akihiko Yoshizawa

IPC分类号： H03L500

CPC分类号： H03F3/45973 ,  H03F3/45475

摘要： An offset compensation circuit comprises an A/D converter, a D/A converter, an attenuator and an analog adder. The A/D converter measures the DC level of an inverting type analog output buffer arranged in an analog signal processing circuit and converts the obtained analog signal into a digital signal. The D/A converter receives the digital signal output from the A/D converter as input and converts the digital signal into an analog signal. The attenuator receives the analog signal output from the D/A converter as input and attenuates its amplitude. The analog adder receives the output signal of the attenuator and that of the analog signal processing circuit as inputs, adds the two signals and supplies the sum signal to the inverting type analog output buffer as input signal of the latter.

公开(公告)号：US06259290B1

公开(公告)日：2001-07-10

申请号：US09332899

申请日：1999-06-15

申请人： Shuichi Takada ,  Akihiko Yoshizawa

发明人： Shuichi Takada ,  Akihiko Yoshizawa

IPC分类号： H03L706

CPC分类号： H03L7/16 ,  H03K5/133 ,  H03L7/0812 ,  H03L7/095 ,  H03L2207/14

摘要： A delay locked loop has a voltage-controlled delay section and a mis-lock detecting circuit. The voltage-controlled delay sections comprises a plurality of controlled delay circuits, including a specific one. In the mis-lock detecting circuit, there are generated pulse signals, each having a pulse width equivalent to the delay time between the delayed signals output from the adjacent two of the controlled delay circuits preceding the specific controlled delayed circuit. Another pulse signal is generated, which has a pulse width equivalent to the delay time between the delayed signals output from adjacent two of the specific controlled delay circuit and the other controlled delay circuits following the specific one. These pulse signals are added, generating a pulse signal. The number of pulses this pulse signal has per a unit time is compared with the number of pulses a reference signal has per the unit time, thereby detecting whether the delay locked loop is normally locked or not.

摘要翻译： 延迟锁定环路具有电压控制延迟部分和误锁检测电路。 电压控制延迟部分包括多个受控延迟电路，包括特定的延迟电路。 在误锁检测电路中，产生脉冲信号，每个脉冲信号的脉冲宽度等于从特定受控延迟电路之前的相邻两个受控延迟电路输出的延迟信号之间的延迟时间。 产生另一个脉冲信号，该脉冲信号的脉冲宽度等于从特定受控延迟电路的相邻两个输出的延迟信号与特定控制延迟电路之后的其它受控延迟电路之间的延迟时间。 添加这些脉冲信号，产生脉冲信号。 将该脉冲信号每单位时间的脉冲数与参考信号每单位时间的脉冲数进行比较，从而检测延迟锁定环是否被正常锁定。

公开(公告)号：US06177846B1

公开(公告)日：2001-01-23

申请号：US09299072

申请日：1999-04-26

申请人： Shuichi Takada ,  Akihiko Yoshizawa

发明人： Shuichi Takada ,  Akihiko Yoshizawa

IPC分类号： H03K302

CPC分类号： H03K3/0315

摘要： A voltage controlled oscillator includes plural cascade-connected unit circuits supplied with selection signals corresponding to an oscillation frequency. Each unit circuit includes a voltage controlled delay circuit, selection circuit and adder circuit. The selection circuit has a first input terminal supplied with an output signal of the voltage controlled delay circuit and a second input terminal supplied with the selection signal. The adder circuit has a first input terminal supplied with an output signal of the selection circuit, a second input terminal supplied with a feedback signal from a next-stage one of the unit circuits and a third input terminal supplied with the selection signal. The adder circuit adds signals supplied to its first and second input terminals to form a feedback signal. The output signal of the voltage controlled delay circuit in each unit circuit is supplied to the voltage controlled delay circuit in the next-stage one of the unit circuits. The output signal of the voltage controlled delay circuit in the unit circuit selected by the selection signal is supplied to the adder circuit via the selection circuit, sequentially supplies the output signal of the adder circuit to the adder circuit in a preceding-stage one of the unit circuits and feeds back the feedback signal output from the adder circuit in the first-stage one of the unit circuits to the input terminal of the voltage controlled delay circuit of the first-stage unit circuit.

摘要翻译： 压控振荡器包括提供有与振荡频率对应的选择信号的多个级联连接单元电路。 每个单元电路包括电压控制延迟电路，选择电路和加法器电路。 选择电路具有被提供有电压控制延迟电路的输出信号的第一输入端和提供有选择信号的第二输入端。 加法器电路具有提供有选择电路的输出信号的第一输入端，提供有来自下一级单电路的反馈信号的第二输入端和提供有选择信号的第三输入端。 加法器电路将提供给其第一和第二输入端的信号相加以形成反馈信号。 每个单位电路中的电压控制延迟电路的输出信号被提供给下一级单元电路中的压控延迟电路。 由选择信号选择的单位电路中的电压控制延迟电路的输出信号通过选择电路提供给加法器电路，将加法器电路的输出信号依次提供给加法器电路的前级 单元电路，将从第一级单位电路中的加法器电路输出的反馈信号反馈到第一级单元电路的电压控制延迟电路的输入端。

公开(公告)号：US6011444A

公开(公告)日：2000-01-04

申请号：US132196

申请日：1998-08-11

申请人： Shuichi Takada ,  Akihiko Yoshizawa

发明人： Shuichi Takada ,  Akihiko Yoshizawa

IPC分类号： H03K3/011 ,  H03K3/03 ,  H03K3/354 ,  H03L7/06 ,  H03L7/099 ,  H03B5/24

CPC分类号： H03L7/0805 ,  H03K3/011 ,  H03K3/0315 ,  H03K3/354 ,  H03L7/0995 ,  H03L2207/06

摘要： An object is to keep the oscillation gain nearly constant and attain an oscillation frequency with high stability and low jitter. A voltage controlled oscillator circuit (VCO) is constructed by a VCO control circuit and a ring oscillator. The VCO control circuit has two input terminals (n input, w input). The VC control circuit multiplies the n input by the w input, and outputs a control signal (PMOS n input, NMOS n input) obtained by adding the result of multiplication to the n input. The ring oscillator is constructed by delay circuits of an odd number of stages serially connected.

摘要翻译： 目的是保持振荡增益几乎恒定，达到稳定性高，抖动小的振荡频率。 压控振荡器电路（VCO）由VCO控制电路和环形振荡器构成。 VCO控制电路有两个输入端子（n个输入端，w个输入端）。 VC控制电路将n输入与w输入相乘，并输出通过将乘法结果与n输入相加而获得的控制信号（PMOS n input，NMOS n input）。 环形振荡器由串联连接的奇数级的延迟电路构成。

公开(公告)号：US5955902A

公开(公告)日：1999-09-21

申请号：US812972

申请日：1997-03-05

申请人： Shuichi Takada ,  Akihiko Yoshizawa

发明人： Shuichi Takada ,  Akihiko Yoshizawa

IPC分类号： H03K3/354 ,  H03B19/00 ,  H03K5/00 ,  H03K19/0948 ,  H03L7/081 ,  H03L7/099 ,  H03L7/16 ,  H03K5/159

CPC分类号： H03K5/00006 ,  H03L7/0812 ,  H03L7/0995 ,  H03L7/16 ,  H03L2207/10

摘要： A voltage controlled delay circuit is comprised of a plurality of stages of delay cells and produces a 2N number of signals delayed behind a reference signal in units of time corresponding to 1/2N the delay time between the reference signal supplied to an input terminal of a first stage delay cell and a signal output from a final stage delay cell. A phase coincidence is achieved between the reference signal and the output signal from the final stage delay cell by a loop including a phase comparator, lowpass filter and voltage controlled delay circuit. An N multiplying logic circuit produces an N multiplied signal from the reference signal with only falls or rises of 2N delay signals.

摘要翻译： 电压控制延迟电路由多级延迟单元组成，并产生延迟在参考信号后面的2N个数字，以对应于1 / 2N的时间为单位，延迟时间在提供给输入端的输入端之间的延迟时间 第一级延迟单元和从最后级延迟单元输出的信号。 通过包括相位比较器，低通滤波器和压控延迟电路的回路，在参考信号和来自最后级延迟单元的输出信号之间实现相位一致。 N乘法逻辑电路从参考信号产生N相乘信号，仅具有2N个延迟信号的下降或上升。

公开(公告)号：US5909474A

公开(公告)日：1999-06-01

申请号：US768633

申请日：1996-12-18

申请人： Akihiko Yoshizawa

发明人： Akihiko Yoshizawa

IPC分类号： H03L7/22 ,  H03L7/07 ,  H03L7/087 ,  H03D3/24

CPC分类号： H03L7/07

摘要： A phase-locked loop (PLL) system including a voltage-controlled oscillator, a divider, a phase detector, and a low-pass filter. The voltage-controlled oscillator has two control input terminals S and L and generates a pulse signal having an oscillation frequency fout2. The divider generates a pulse signal having a frequency fout2/N2 from the output signal of the oscillator. The phase detector detects the phase difference between the pulse signal output from the divider and the a pulse signal having a reference frequency fref and generates an error signal corresponding to the phase difference detected. The low-pass filter integrates the error signal. The output signal of the low-pass filter is input to the control input terminal S of the oscillator. A control signal is input to the control input terminal L of the oscillator to control the free-running frequency of the oscillator.

摘要翻译： 一种锁相环（PLL）系统，包括压控振荡器，分频器，相位检测器和低通滤波器。 压控振荡器具有两个控制输入端子S和L，并产生具有振荡频率fout2的脉冲信号。 分频器从振荡器的输出信号产生具有频率fout2 / N2的脉冲信号。 相位检测器检测从分频器输出的脉冲信号与具有参考频率fref的脉冲信号之间的相位差，并产生与所检测的相位差对应的误差信号。 低通滤波器集成了误差信号。 低通滤波器的输出信号输入到振荡器的控制输入端子S. 控制信号被输入到振荡器的控制输入端子L，以控制振荡器的自由运行频率。

公开(公告)号：US5594391A

公开(公告)日：1997-01-14

申请号：US229791

申请日：1994-04-19

申请人： Akihiko Yoshizawa

发明人： Akihiko Yoshizawa

IPC分类号： H03K3/03 ,  H03K3/354 ,  H03L7/099 ,  H03B5/00

CPC分类号： H03K3/354 ,  H03K3/0315

摘要： A VCO includes an oscillator and a controller for controlling the operation of the oscillator. The oscillator is formed by connecting odd number of stages of delay circuits in a ring form. The controller creates a second control voltage based on an input first control voltage. The second control voltage is set in a symmetrical relation to the first control voltage with respect to an intermediate potential between the power supply and the ground set as a reference. Each of the delay circuits includes an inverter, first and second current control circuits, and first and second current value setting circuits. The inverter includes a first transistor of first conductivity type and a second transistor of second conductivity type to receive and output a signal. The first current control circuit is connected between the first transistor and the ground, for controlling a current flowing in the first transistor when the first transistor is set in the conductive state according to the first control voltage. The first current value setting circuit sets the minimum value of the current flowing in the first transistor. The second current control circuit is connected between the second transistor and the power supply, for controlling a current flowing in the second transistor when the second transistor is set in the conductive state according to the second control voltage. The second current value setting circuit sets the minimum value of the current flowing in the second transistor.

摘要翻译： VCO包括用于控制振荡器的操作的振荡器和控制器。 振荡器通过连接奇数级的延迟电路以环形形成。 控制器基于输入的第一控制电压产生第二控制电压。 第二控制电压相对于作为基准的电源和地面之间的中间电位以第一控制电压为对称关系。 每个延迟电路包括反相器，第一和第二电流控制电路以及第一和第二电流值设定电路。 逆变器包括第一导电类型的第一晶体管和第二导电类型的第二晶体管，用于接收和输出信号。 第一电流控制电路连接在第一晶体管和地之间，用于当第一晶体管根据第一控制电压设置在导通状态时控制在第一晶体管中流动的电流。 第一电流值设定电路设定流过第一晶体管的电流的最小值。 第二电流控制电路连接在第二晶体管和电源之间，用于当根据第二控制电压将第二晶体管设置在导通状态时控制在第二晶体管中流动的电流。 第二电流值设定电路设定流过第二晶体管的电流的最小值。

公开(公告)号：US5432760A

公开(公告)日：1995-07-11

申请号：US55906

申请日：1993-05-03

申请人： Akihiko Yoshizawa ,  Yasuhiro Fujiwara

发明人： Akihiko Yoshizawa ,  Yasuhiro Fujiwara

IPC分类号： G01N21/21 ,  G01N21/23 ,  G11B7/135 ,  G11B11/10 ,  G11B11/105 ,  G11B11/00

CPC分类号： G01N21/23 ,  G11B11/10543 ,  G11B11/10582 ,  G11B7/1369

摘要： In order to measure a phase difference of an opto-magnetic disk having a substrate and a magnetic record layer, linearly polarized light is made incident upon the magnetic layer of the disk from the side of the substrate and light reflected by the disk is received to derive an information signal recorded in the disk, while the opto-magnetic disk is rotated at a usual reproducing speed. A phase compensator arranged in an optical path of the light reflected by the disk is adjusted to change a phase difference introduced by the phase compensator into the light reflected by the disk, while a level of amplitude and/or C/N of the reproduced information signal is monitored. A value of the phase difference introduced by the phase compensator when the amplitude and/or C/N of the reproduced information signal becomes maximum is derived as a measured phase difference of the opto-magnetic disk.

摘要翻译： 为了测量具有基板和磁记录层的光磁盘的相位差，线性偏振光从基板侧入射到盘的磁性层上，并且被盘反射的光被接收到 导出记录在盘中的信息信号，同时光盘以通常的再现速度旋转。 调整布置在由盘反射的光的光路中的相位补偿器，以将由相位补偿器引入的相位差改变为由盘反射的光，同时再现信息的幅度和/或C / N的电平 信号被监视。 当再现信息信号的幅度和/或C / N变为最大时，由相位补偿器引入的相位差的值被导出为光磁盘的测量相位差。