公开(公告)号：US5241222A

公开(公告)日：1993-08-31

申请号：US810978

申请日：1991-12-20

申请人： Jeffrey A. Small ,  Alan T. Torok

发明人： Jeffrey A. Small ,  Alan T. Torok

IPC分类号： G06F12/02 ,  G06F12/04 ,  G11C7/22 ,  G11C11/401

CPC分类号： G11C7/22

摘要： The present invention is an interface adapter circuit that allows multiple types of 256K by 16 bit dynamic random random access memories to be used by system manufacturers. The interface adapter circuit selects a type of outputs signal set to produce responsive to a mode selection signal. The circuit converts an input signal set including a column address probe and low and high by write signals into either a first output signal set, including one column address strobe and high and low byte write signals, or a second output signal set including a single write signal and high and low column address signals, responsive to the selection signal. The circuit includes a logic circuit for producing the signals and flip flops for holding the signal produced. The flip flops also synchronize other memory address, etc. signals with the signals produced by the adapter circuit. The interface adapter circuit can also convert write nd column address timing signals and low and high byte write signals into the two sets responsive to a selection signal.

公开(公告)号：US06272465B1

公开(公告)日：2001-08-07

申请号：US08934969

申请日：1997-09-22

申请人： Larry D. Hewitt ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Michael Hogan ,  Alfredo R. Linz ,  David Norris ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

发明人： Larry D. Hewitt ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Michael Hogan ,  Alfredo R. Linz ,  David Norris ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

IPC分类号： G10L500

CPC分类号： H03K23/68 ,  G06F3/162 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

摘要翻译： 用于在个人计算机中提供增强音频性能的单片集成电路。 单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

公开(公告)号：US5659466A

公开(公告)日：1997-08-19

申请号：US333536

申请日：1994-11-02

申请人： David Norris ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Larry D. Hewitt ,  Michael Hogan ,  Alfredo R. Linz ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

发明人： David Norris ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Larry D. Hewitt ,  Michael Hogan ,  Alfredo R. Linz ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

IPC分类号： G06F3/16 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  H03K23/68

CPC分类号： H03K23/68 ,  G06F3/162 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/611

摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects