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    Apparatus and method for a combination D/A converter and FIR filter employing active current division from a single current source
    4.
    发明授权
    Apparatus and method for a combination D/A converter and FIR filter employing active current division from a single current source 失效
    用于组合D / A转换器和FIR滤波器的装置和方法，其采用来自单个电流源的有源电流分配

    公开(公告)号：US5995030A

    公开(公告)日：1999-11-30

    申请号：US526834

    申请日：1995-09-12

    申请人： Carlin Dru Cabler

    发明人： Carlin Dru Cabler

    IPC分类号： H03H17/02 ,  H03H17/06 ,  H03M1/74 ,  H03M3/02 ,  H03M1/66

    CPC分类号： H03H17/0289 ,  H03M1/745 ,  H03M3/504

    摘要： An active current steering semi-digital FIR filter for a digital-to-analog conversion circuit, which includes a shift register having a 1-bit digital input stream and a plurality of output taps, where each output tap provides a 1-bit signal which has a value of a logic 1 or a logic 0, and a plurality of current paths, where each path includes an active element, such as a transistor, having a relatively high output impedance, which is connected to a common current source, and to an op amp for current-to-voltage conversion. The relatively high output impedance of the active current steering element causes any error term resulting from offset at the op amp inputs to be minimized.

    摘要翻译： 一种用于数模转换电路的有源电流转向半数字FIR滤波器，其包括具有1位数字输入流和多个输出抽头的移位寄存器，其中每个输出抽头提供1位信号， 具有逻辑1或逻辑0的值，以及多个电流路径，其中每个路径包括连接到公共电流源的具有相对较高输出阻抗的有源元件，例如晶体管，并且 用于电流至电压转换的运算放大器。 有源电流导向元件的相对高的输出阻抗导致由运算放大器输入端的偏移导致的任何误差项都被最小化。

    Digital method to eliminate power-on pops and clicks
    5.
    发明授权
    Digital method to eliminate power-on pops and clicks 失效
    数字方式消除上电弹出和点击

    公开(公告)号：US5796851A

    公开(公告)日：1998-08-18

    申请号：US760760

    申请日：1996-12-05

    申请人： Larry Hewitt ,  Carlin Dru Cabler

    发明人： Larry Hewitt ,  Carlin Dru Cabler

    IPC分类号： H03G3/34 ,  H03M1/08 ,  H03M1/66 ,  H04B15/00

    CPC分类号： H03M1/0881 ,  H03G3/348 ,  H03M1/66

    摘要： A personal computer audio system is presented with a mechanism for digitally regulating the rate of voltage change of an audio output signal In one embodiment, the audio output signal from an integrated circuit is provided by means of a two-state audio amplifier. The first state of the amplifier is a high impedance state which exists prior to power-on and is maintained until an enable signal is asserted. When the enable signal is asserted, the amplifier drives the audio output signal line. Prior to the transition from the first to second states, a D/A converter is used to provide a ramp signal from the minimum voltage to the nominal operating voltage. The state transition is then initiated during the initial portion of the ramp signal.

    摘要翻译： 具有用于数字调节音频输出信号的电压变化速率的机构的个人计算机音频系统。在一个实施例中，来自集成电路的音频输出信号通过双状态音频放大器提供。 放大器的第一状态是在上电之前存在的高阻抗状态，并且保持到使能信号被断言为止。 当使能信号置位时，放大器驱动音频输出信号线。 在从第一状态转换到第二状态之前，使用D / A转换器来提供从最小电压到标称工作电压的斜坡信号。 然后在斜坡信号的初始部分期间启动状态转换。

    Sigma-delta modulator having reduced delay from input to output
    6.
    发明授权
    Sigma-delta modulator having reduced delay from input to output 失效
    Sigma-delta调制器具有从输入到输出的延迟降低

    公开(公告)号：US5648779A

    公开(公告)日：1997-07-15

    申请号：US352665

    申请日：1994-12-09

    申请人： Carlin Dru Cabler

    发明人： Carlin Dru Cabler

    IPC分类号： H03M3/02 ,  H03M7/00

    CPC分类号： H03M7/3006 ,  H03M3/418 ,  H03M7/3022

    摘要： Described herein is a fourth-order sigma-delta modulator which utilizes two second-order sigma-delta modulators connected together. Each second-order sigma-delta modulator is characterized as including integrators having a 1/2 sample period delay from input to output. A second-order sigma-delta modulator, including such integrators, exhibits a single sample period delay from input to output. A fourth-order sigma-delta modulator, which includes two such second-order sigma-delta modulators, exhibits a delay of two sample periods from input to output. The present sigma-delta modulator can be fabricated using switched capacitor circuitry to form an A/D convertor, and in another embodiment can be used as a digital noise shaper for a D/C convertor circuit. The 1/2 unit delay is implemented without requiring two D-flip flops in series, which results in a design and manufacturing advantage.

    摘要翻译： 这里描述的是利用连接在一起的两个二阶Σ-Δ调制器的四阶Σ-Δ调制器。 每个二阶Σ-Δ调制器的特征在于包括具有从输入到输出的+ E，fra 1/2 + EE采样周期延迟的积分器。 包括这种积分器的二阶Σ-Δ调制器表现出从输入到输出的单个采样周期延迟。 包括两个这样的二阶Σ-Δ调制器的四阶Σ-Δ调制器表现出从输入到输出的两个采样周期的延迟。 可以使用开关电容器电路来制造现有的Σ-Δ调制器以形成A / D转换器，并且在另一实施例中可以将其用作D / C转换器电路的数字噪声整形器。 + E，fra 1/2 + EE单位延迟实现，而不需要两个D触发器串联，这导致设计和制造优势。