公开(公告)号：US5678048A

公开(公告)日：1997-10-14

申请号：US433757

申请日：1995-05-04

申请人： Brett Stewart ,  Ryan Feemster

发明人： Brett Stewart ,  Ryan Feemster

IPC分类号： G06F9/32 ,  G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/32 ,  G06F9/322

摘要： An interrupt vector approach for a processor system loads an interrupt vector directly into an address. register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

摘要翻译： 处理器系统的中断向量方法将中断向量直接加载到地址中。 注册以最小化处理中断的开销。 多个中断触发对应于多个中断向量寄存器，每个中断向量寄存器包含可编程中断向量。 激活一个中断触发后，相应的中断向量的内容将被加载到一个插槽内存地址计数器中。 地址计数器寻址定序器时隙存储器，其包含存储在指令存储器中的指令序列的起始地址。 指令地址计数器从定序器时隙存储器接收地址，并向指令存储器提供地址。 在激活所述中断触发中的一个时，开始从与活动中断触发相对应的中断寄存器中包含的地址开始的序列中的一个序列的执行，并且定序器时隙存储器中的序列的地址被顺序地加载到指令地址 计数器，直到定序器插槽存储器中的一个字中指示停止位。

公开(公告)号：US5608873A

公开(公告)日：1997-03-04

申请号：US675217

申请日：1996-07-03

申请人： Ryan Feemster ,  David Dettmer

发明人： Ryan Feemster ,  David Dettmer

IPC分类号： G06F15/167 ,  G06F13/14

CPC分类号： G06F15/167

摘要： A device and method for providing inter-processor communication in a multi-processor architecture. A post office RAM has a plurality of mailboxes. Each mailbox is write-accessible by one port, but is read-accessible by the other ports. Thus, a processor device on a port has write-access to one mailbox, but can read the other mailboxes in the post office. A transmitting processor communicates with a receiving processor, by utilizing the post office. The transmitting processor writes information into its own mailbox, and signals a receiving processor. The receiving processor determines which of the processor devices signalled it, and reads the information in the transmitting processor's mailbox.

摘要翻译： 一种用于在多处理器架构中提供处理器间通信的设备和方法。 邮局RAM具有多个邮箱。 每个邮箱都可以由一个端口写入，但可以由其他端口读取。 因此，端口上的处理器设备具有对一个邮箱的写入访问权限，但可以读取邮局中的其他邮箱。 发送处理器通过利用邮局与接收处理器进行通信。 发送处理器将信息写入其自己的邮箱，并向接收处理器发信号。 接收处理器确定哪个处理器设备发出信号，并读取发送处理器的邮箱中的信息。

公开(公告)号：US5557764A

公开(公告)日：1996-09-17

申请号：US433758

申请日：1995-05-04

申请人： Brett Stewart ,  Ryan Feemster

发明人： Brett Stewart ,  Ryan Feemster

IPC分类号： G06F9/32 ,  G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/32 ,  G06F9/322

摘要： An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

公开(公告)号：US5546039A

公开(公告)日：1996-08-13

申请号：US423059

申请日：1995-04-17

申请人： Larry D. Hewitt ,  Ryan Feemster

发明人： Larry D. Hewitt ,  Ryan Feemster

IPC分类号： G06F3/16 ,  G06F7/02 ,  G06F9/38 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  G10H7/02 ,  H03K23/68 ,  H03M3/02 ,  H03M7/32 ,  H03K17/16 ,  H03K5/12

CPC分类号： G06F3/16 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  H03K23/68 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

摘要： A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

摘要翻译： 触发电路的级联顺序地激活一系列平行的下拉路径，该反向响应反应于指示电容负载端口上的电位与可选阈值电压之间的对应关系的下拉信号。 触发电路用公共信号计时，从而在随后的触发级之前顺序地传播下拉信号以顺序激活相应的并行路径。 在优选实施例中，顺序级联的D触发器控制多个下拉路径，以调节单​​片音频个人计算机IC游戏端口上的操纵杆电容负载的充电和放电。 为了启动操纵杆电容器的充电，触发器响应于系统写信号同时禁用下拉路径。 为了放电操纵杆电容器，触发器顺序地传播比较器导出的下拉信号，以顺序使得下拉路径可控制地耗散累积的电荷。

公开(公告)号：US06272465B1

公开(公告)日：2001-08-07

申请号：US08934969

申请日：1997-09-22

申请人： Larry D. Hewitt ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Michael Hogan ,  Alfredo R. Linz ,  David Norris ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

发明人： Larry D. Hewitt ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Michael Hogan ,  Alfredo R. Linz ,  David Norris ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

IPC分类号： G10L500

CPC分类号： H03K23/68 ,  G06F3/162 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

摘要翻译： 用于在个人计算机中提供增强音频性能的单片集成电路。 单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

公开(公告)号：US5659466A

公开(公告)日：1997-08-19

申请号：US333536

申请日：1994-11-02

申请人： David Norris ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Larry D. Hewitt ,  Michael Hogan ,  Alfredo R. Linz ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

发明人： David Norris ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Larry D. Hewitt ,  Michael Hogan ,  Alfredo R. Linz ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

IPC分类号： G06F3/16 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  H03K23/68

CPC分类号： H03K23/68 ,  G06F3/162 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/611

摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

公开(公告)号：US5473763A

公开(公告)日：1995-12-05

申请号：US100152

申请日：1993-08-02

申请人： Brett Stewart ,  Ryan Feemster

发明人： Brett Stewart ,  Ryan Feemster

IPC分类号： G06F9/32 ,  G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/32 ,  G06F9/322

摘要： An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

摘要翻译： 处理器系统的中断向量方法将中断向量直接加载到地址寄存器中以最小化处理中断的开销。 多个中断触发对应于多个中断向量寄存器，每个中断向量寄存器包含可编程中断向量。 激活一个中断触发后，相应的中断向量的内容将被加载到一个插槽内存地址计数器中。 地址计数器寻址定序器时隙存储器，其包含存储在指令存储器中的指令序列的起始地址。 指令地址计数器从定序器时隙存储器接收地址，并向指令存储器提供地址。 在激活所述中断触发中的一个时，开始从与活动中断触发相对应的中断寄存器中包含的地址开始的序列中的一个序列的执行，并且定序器时隙存储器中的序列的地址被顺序地加载到指令地址 计数器，直到定序器插槽存储器中的一个字中指示停止位。