公开(公告)号：US06295011B1

公开(公告)日：2001-09-25

申请号：US08919958

申请日：1997-08-29

申请人： Glen W. Brown

发明人： Glen W. Brown

IPC分类号： H03M702

CPC分类号： G06T1/20 ,  H03H17/0225 ,  H03H17/0657 ,  H03H17/0664 ,  H03H2017/0298

摘要： The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

摘要翻译： 本发明是用于实现数字抽取滤波器和/或数字内插滤波器以及对进行n / 2次加法的抽取和/或内插多位输入信号的方法，其中n = 每个滤波系数。 使用公共DSP架构来执行数据与系数的缩放和乘法。 具有相关比例因子的系数值被存储在存储器中。 系数以编码形式存储，然后在乘以数据值之前被解码。

公开(公告)号：US06272465B1

公开(公告)日：2001-08-07

申请号：US08934969

申请日：1997-09-22

申请人： Larry D. Hewitt ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Michael Hogan ,  Alfredo R. Linz ,  David Norris ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

发明人： Larry D. Hewitt ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Michael Hogan ,  Alfredo R. Linz ,  David Norris ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

IPC分类号： G10L500

CPC分类号： H03K23/68 ,  G06F3/162 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

摘要： A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

摘要翻译： 用于在个人计算机中提供增强音频性能的单片集成电路。 单片电路包括波形合成器; 全功能立体声编解码电路，包括模数转换和数模转换; 数据压缩，模拟信号的混合和复用; 用于与外部存储器接口的本地存储器控制模块; 一个游戏MIDI口模块; 一个系统总线接口; 以及用于兼容性和电路控制功能的控制模块。

公开(公告)号：US06226356B1

公开(公告)日：2001-05-01

申请号：US09097031

申请日：1998-06-12

申请人： Glen W. Brown

发明人： Glen W. Brown

IPC分类号： H04M124

CPC分类号： H04B3/04 ,  H04M3/306

摘要： A method and apparatus is provided for regulating transmission power of a signal on a line. The method includes determining characteristics of the line, determining the transmission power needed to transmit the signal in response to the characteristics of the line, and transmitting the signal on the line in response to determining the transmission power.

摘要翻译： 提供了一种用于调节线路上的信号的发射功率的方法和装置。 该方法包括确定线路的特性，响应于该线路的特性确定发送信号所需的发送功率，以及响应于确定发送功率而在该线路上发送该信号。

公开(公告)号：US5872993A

公开(公告)日：1999-02-16

申请号：US980579

申请日：1997-12-01

申请人： Glen W. Brown

发明人： Glen W. Brown

IPC分类号： G06F9/38 ,  G06F13/00

CPC分类号： G06F9/3877

摘要： The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a microcontroller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

摘要翻译： 本发明包括涉及嵌入式数字信号处理器（DSP），DSP接口和存储架构，微控制器接口，DSP操作系统（OS），数据流模型和用于硬件块的接口的架构。 该设计允许软件在使用硬件来提供有效的数据流，信号处理和存储器访问的同时控制架构的大部分配置。 在具有嵌入式DSP的器件中，存储器访问通常是瓶颈，并与设计的效率紧密耦合。 平台架构涉及允许与其他定制硬件块或微控制器共享DSP存储器的方法。 DSP可以以每百万条指令每秒运行一次（MIPS），而另一个功能则是将数据传输到内存或从内存传输数据。 这样可以有效地利用存储器以及在软件和硬件之间分配DSP任务。

公开(公告)号：US5809466A

公开(公告)日：1998-09-15

申请号：US753719

申请日：1996-11-27

申请人： Larry D. Hewitt ,  Glen W. Brown ,  Dale E. Gulick ,  Michael Hogan ,  David Norris ,  Martin P. Soques ,  David N. Suggs

发明人： Larry D. Hewitt ,  Glen W. Brown ,  Dale E. Gulick ,  Michael Hogan ,  David Norris ,  Martin P. Soques ,  David N. Suggs

IPC分类号： G06F7/02 ,  H03K23/68 ,  G10L5/00

CPC分类号： H03K23/68 ,  G06F7/026

摘要： This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.

摘要翻译： 本发明是用于单个单片音频处理集成电路，其包括CODEC模块中的合成器模块，CODEC模块和外部串行数据端口，用于CODEC模块和外部串行数据设备之间的双向串行数据通信，例如 数字信号处理器。 还包括合成器模块和CODEC模块之间的串行数据路径。

公开(公告)号：US5732004A

公开(公告)日：1998-03-24

申请号：US555685

申请日：1995-11-14

申请人： Glen W. Brown

发明人： Glen W. Brown

IPC分类号： G06T1/20 ,  G06F17/10 ,  G06F17/17

CPC分类号： G06T1/20 ,  H03H17/0225 ,  H03H17/0657 ,  H03H17/0664 ,  H03H2017/0298

摘要： The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

摘要翻译： 本发明是用于实现数字抽取滤波器和/或数字内插滤波器的方法，以及一种抽取和/或内插多位输入信号的方法，其中执行n / 2次加法，其中n = 每个滤波系数。 使用公共DSP架构来执行数据与系数的缩放和乘法。 具有相关比例因子的系数值被存储在存储器中。 系数以编码形式存储，然后在乘以数据值之前被解码。

公开(公告)号：US5659466A

公开(公告)日：1997-08-19

申请号：US333536

申请日：1994-11-02

申请人： David Norris ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Larry D. Hewitt ,  Michael Hogan ,  Alfredo R. Linz ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

发明人： David Norris ,  Jeffrey M. Blumenthal ,  Geoffrey E. Brehmer ,  Glen W. Brown ,  Carlin Dru Cabler ,  Ryan Feemster ,  David Guercio ,  Dale E. Gulick ,  Larry D. Hewitt ,  Michael Hogan ,  Alfredo R. Linz ,  Paul G. Schnizlein ,  Martin P. Soques ,  Michael E. Spak ,  David N. Suggs ,  Alan T. Torok

IPC分类号： G06F3/16 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  H03K23/68

CPC分类号： H03K23/68 ,  G06F3/162 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/611

摘要： A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

公开(公告)号：US5589830A

公开(公告)日：1996-12-31

申请号：US333467

申请日：1994-11-02

申请人： Alfredo R. Linz ,  Carlin D. Cabler ,  Glen W. Brown ,  Martin P. Soques

发明人： Alfredo R. Linz ,  Carlin D. Cabler ,  Glen W. Brown ,  Martin P. Soques

IPC分类号： F02B75/02 ,  G06F3/16 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  H03K23/68 ,  H03M7/32 ,  H03M1/00

CPC分类号： H03K23/68 ,  G06F3/162 ,  G10H1/0058 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  F02B2075/027 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/115 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/611

摘要： A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.

摘要翻译： 立体声音频CODEC，包括用于执行D / A和A / D转换的装置，用于在衰减/增益变化期间减少数字感应噪声的装置，数据格式转换装置，模拟和数字滤波装置，模拟混合装置，片上16- 采样，32位宽记录和播放FIFO，与外部串行DSP的串行接口，用于补充片上记录和播放FIFO，控制寄存器，寄存器数据总线和合成器DAC的大型本地存储器。

公开(公告)号：US5195050A

公开(公告)日：1993-03-16

申请号：US570187

申请日：1990-08-20

申请人： Ken W. Hsu ,  Lionel J. D'Luna ,  Hur Jay Yeh ,  Glen W. Brown

发明人： Ken W. Hsu ,  Lionel J. D'Luna ,  Hur Jay Yeh ,  Glen W. Brown

IPC分类号： G06F17/16 ,  G06T5/20

CPC分类号： G06F17/16

摘要： An integrated circuit that uses the same coefficient registers, multipliers and adders to perform both matrix multiplication and convolution operations. The multipliers are arranged in columns and rows with the matrix multiplication adders located in the corresponding columns and with the adder for producing the convolution output located in one of the columns. A mode selection switch causes the multiplexers to change input data routing based on the mode selected. The circuit allows loading of all the coefficients or selection of hardwired coefficients. By rerouting the inputs of the multipliers using the multiplexers, the circuit can be easily configured for either mode of operation. The outputs corresponding to the columns are either output directly during matrix multiplication or provided to the convolution adder. The provision of an internal pseudo random number generator, serial inputs and outputs for test data and a signature analysis signal generating circuit allows the circuit to be easily internally tested.

摘要翻译： 使用相同系数寄存器，乘法器和加法器执行矩阵乘法和卷积运算的集成电路。 乘法器以列和行排列，矩阵乘法加法器位于相应的列中，并且加法器用于产生位于列之一中的卷积输出。 模式选择开关使得多路复用器基于所选择的模式改变输入数据路由。 电路允许加载所有系数或选择硬连线系数。 通过使用多路复用器重新路由乘法器的输入，可以容易地为任一种操作模式配置该电路。 对应于列的输出在矩阵乘法期间直接输出或提供给卷积加法器。 提供内部伪随机数发生器，用于测试数据的串行输入和输出以及签名分析信号发生电路允许电路容易地在内部测试。

公开(公告)号：US6029239A

公开(公告)日：2000-02-22

申请号：US980580

申请日：1997-12-01

申请人： Glen W. Brown

发明人： Glen W. Brown

IPC分类号： G06F9/50 ,  H04L12/56 ,  G06F15/00

CPC分类号： H04L49/9089 ,  G06F9/5016 ,  H04L12/5693 ,  H04L47/522 ,  H04L49/90 ,  H04L49/901

摘要： A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

摘要翻译： 通信系统利用嵌入式数字信号处理器（DSP），DSP接口和存储架构，微控制器接口，DSP操作系统（OS），数据流模型和硬件块接口。 该设计允许软件在使用硬件来提供有效的数据流，信号处理和存储器访问的同时控制架构的大部分配置。 在具有嵌入式DSP的器件中，存储器访问通常是瓶颈，并与设计的效率紧密耦合。 平台架构涉及允许与其他定制硬件块或微控制器共享DSP存储器的方法。 DSP可以以每百万条指令每秒运行一次（MIPS），而另一个功能则是将数据传输到内存或从内存传输数据。 这样可以有效地利用存储器以及在软件和硬件之间分配DSP任务。