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    Double time-constant for electrostatic discharge clamping
    1.
    发明授权
    Double time-constant for electrostatic discharge clamping 失效
    用于静电放电钳位的双倍时间常数

    公开(公告)号：US06917207B1

    公开(公告)日：2005-07-12

    申请号：US10745382

    申请日：2003-12-22

    申请人： Jeffrey M. Blumenthal

    发明人： Jeffrey M. Blumenthal

    IPC分类号： H02H1/04 ,  H02H9/04 ,  G01R27/26 ,  H02H9/00

    CPC分类号： H02H9/046 ,  H02H1/04

    摘要： A method and apparatus is provided for clamping of an electrostatic discharge using multiple time-constants. A rise in a voltage level is detected. A first time-constant is provided to determine whether the rise in the voltage level is caused by an electrostatic event. A clamping function is provided to clamp the voltage level in response to a determination that the rise in the voltage level is caused by the electrostatic event. A second time-constant is provided to provide a time period for maintaining the clamping function for a period of time to substantially extinguish the electrostatic event.

    摘要翻译： 提供了一种使用多个时间常数来夹持静电放电的方法和装置。 检测到电压电平的上升。 提供第一时间常数以确定电压电平的上升是否由静电事件引起。 提供钳位功能以响应于电压电平的上升是由静电事件引起的确定来钳位电压电平。 提供第二时间常数以提供用于将夹持功能保持一段时间以显着熄灭静电事件的时间段。

    Enhanced register array accessible by both a system microprocessor and a wavetable audio synthesizer
    2.
    发明授权
    Enhanced register array accessible by both a system microprocessor and a wavetable audio synthesizer 有权
    增强的寄存器阵列可由系统微处理器和波形音频合成器访问

    公开(公告)号：US6058066A

    公开(公告)日：2000-05-02

    申请号：US160992

    申请日：1998-09-25

    申请人： David E. Norris ,  Larry D. Hewitt ,  Jeffrey M. Blumenthal

    发明人： David E. Norris ,  Larry D. Hewitt ,  Jeffrey M. Blumenthal

    IPC分类号： G06F3/16 ,  G06F7/02 ,  G06F9/38 ,  G10H1/00 ,  G10H1/12 ,  G10H7/00 ,  G10H7/02 ,  H03K23/68 ,  H03M3/02 ,  H03M7/32 ,  G11C8/00

    CPC分类号： H03K23/68 ,  G06F3/162 ,  G06F7/026 ,  G06F9/3869 ,  G10H1/0066 ,  G10H1/125 ,  G10H7/002 ,  G10H7/02 ,  G10H2220/315 ,  G10H2230/035 ,  G10H2240/311 ,  G10H2250/191 ,  G10H2250/545 ,  G10H2250/571 ,  G10H2250/605 ,  G10H2250/611

    摘要： A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.

    摘要翻译： 一种可由PC音频电路的系统微处理器和数字信号处理器访问的寄存器阵列，包括：（i）具有连接到数字信号处理器输入/输出端口的第一端口的随机存取存储器（RAM），以及第二 端口连接到RAM输入/输出端口; （ii）连接到RAM输入/输出端口并具有到寄存器数据总线的连接的寄存器数据端口; （iii）用于定时寄存器阵列操作的定时电路; （iv）用于分别在所述RAM中选择行和列的行和列选择电路; 和（v）连接到所述定时电路的输入/输出通道就绪信号线。 RAM包括多个边沿位，每个边沿位存储指示存储在所述RAM中的一行数据值的处理是处于活动还是非活动状态的值。 当RAM不空闲或微处理器寻求访问当前受数字信号处理器访问的RAM的一行时，系统微处理器被禁止访问RAM。 如果微处理器禁止向RAM写入数据，则数据可能会临时存储在寄存器数据端口中，直到微处理器的访问被使能为止。

    Automatic polarity detection and correction method and apparatus employing linkpulses
    3.
    发明授权
    Automatic polarity detection and correction method and apparatus employing linkpulses 失效
    采用连续脉冲的自动极性检测和校正方法及装置

    公开(公告)号：US5257287A

    公开(公告)日：1993-10-26

    申请号：US620980

    申请日：1990-11-30

    申请人： Jeffrey M. Blumenthal ,  Nader Vijeh ,  John M. Wincn ,  Ian S. Crayford

    发明人： Jeffrey M. Blumenthal ,  Nader Vijeh ,  John M. Wincn ,  Ian S. Crayford

    IPC分类号： H03M7/00 ,  H03K5/02 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/156 ,  H03K19/0185 ,  H03M5/12 ,  H04L25/02 ,  H04L25/08 ,  H04L25/49 ,  H04L25/34

    CPC分类号： H03K5/023 ,  H03K19/018578 ,  H03K5/13 ,  H03K5/1534 ,  H03K5/156 ,  H04L25/02 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/08 ,  H04L25/085 ,  H04L25/4904

    摘要： A differential receiver incorporated into a MAU which receives both Manchester packets and linkpulses according to the IEEE 802.3 10Base-T standard has polarity detection and correction circuit for automatically detecting a reversed polarity for RD input lines. The differential receiver samples incoming pulses for time, amplitude and pulse width qualification and makes a preliminary polarity determination based upon polarity of such qualified pulses. This preliminary polarity allows a linktest state machine to transition to a link.sub.-- pass state, enabling output drivers of the MAU. Additionally, the linkpulse polarity information initially makes a polarity determination for the entire differential receiver which asserts a FIX POLARITY signal. The FIX POLARITY signal controls a correction circuit which internally remedies reversed input lines. Preferably, the correction circuit internally reroutes the signals. An ETD polarity circuit makes polarity determinations from any ETD information received, as effected by the correction circuit. The ETD polarity circuit independently controls the linkpulse polarity determinations and conflicting determinations are resolved in favor of the ETD polarity circuit. Upon detecting two consecutive, consistent valid ETDs, the ETD polarity circuit locks-in the polarity determinations until a reset or a linkfail condition. The correction circuit effects both Manchester packets and linkpulses, so an incorrectly locked polarity will produce inverted linkpulses which will not allow the MAU to remain in the link.sub.-- pass state. In the linkfail state, the MAU may reestablish the correct polarity.

    摘要翻译： 根据IEEE 802.3 10Base-T标准，并入到接收曼彻斯特分组和链路脉冲的MAU中的差分接收机具有用于自动检测RD输入线的反极性的极性检测和校正电路。 差分接收器对输入脉冲进行时间，幅度和脉冲宽度鉴定，并根据这种合格脉冲的极性进行初步极性判定。 该初步极性允许链路测试状态机转换到链路通过状态，使得MAU的输出驱动器成为可能。 此外，链路脉冲极性信息最初对整个差分接收机进行极性确定，这个确定了FIX POLARITY信号。 FIX POLARITY信号控制一个校正电路，内部补救反向输入线路。 优选地，校正电路在内部重新路由信号。 ETD极性电路根据校正电路实现的任何接收的ETD信息进行极性判定。 ETD极性电路独立控制链路脉冲极性判定，冲突确定有利于ETD极性电路。 在检测到两个连续的，一致的有效ETD时，ETD极性电路锁定极性确定，直到复位或链接状态。 校正电路影响曼彻斯特数据包和链路脉冲，因此锁定不正确的极性将产生反向的链路脉冲，这将不允许MAU保持链路通过状态。 在链接状态下，MAU可能会重新建立正确的极性。

    AUI to twisted pair loopback
    6.
    发明授权
    AUI to twisted pair loopback 失效
    AUI双绞线环回

    公开(公告)号：US5467369A

    公开(公告)日：1995-11-14

    申请号：US224946

    申请日：1994-04-08

    申请人： Nader Vijeh ,  Ian S. Crayford ,  Jeffrey M. Blumenthal

    发明人： Nader Vijeh ,  Ian S. Crayford ,  Jeffrey M. Blumenthal

    IPC分类号： G06F13/00 ,  H03K5/02 ,  H03K5/156 ,  H03K19/0185 ,  H04L25/02 ,  H04L25/08 ,  H04L25/49 ,  H04B3/46 ,  H04B17/00

    CPC分类号： H04L25/028 ,  H03K19/018578 ,  H03K5/023 ,  H03K5/156 ,  H04L25/0272 ,  H04L25/08 ,  H04L25/085 ,  H04L25/4904 ,  H04L25/0292

    摘要： An integrated media attachment unit (MAU) operative for interfacing Digital Terminal Equipment (DTE) on a Local Area Network (LAN) using twisted pair media. The twisted pair function as either a DTE MAU or a repeater MAU. A line driver for the twisted pair differential signal provides a ramped response with low jitter while an improved Attachment Unit Interface (AUI) driver uses CMOS technology and provides simplified End-of-Transmission Delimiter (ETD) control. The twisted pair MAU includes a combined override and status indication of link status and an additional feature to allow automatic polarity reversal of differential signal input lines and polarity status signalling.

    摘要翻译： 用于使用双绞线介质在局域网（LAN）上连接数字终端设备（DTE）的集成媒体附件单元（MAU）。 双绞线用作DTE MAU或中继器MAU。 双绞线差分信号的线路驱动器提供具有低抖动的斜坡响应，而改进的附件单元接口（AUI）驱动器使用CMOS技术并提供简化的终止传输定界符（ETD）控制。 双绞线MAU包括链路状态的组合覆盖和状态指示以及允许差分信号输入线自动极性反转和极性状态信号的附加功能。