公开(公告)号：US06734490B2

公开(公告)日：2004-05-11

申请号：US09919341

申请日：2001-07-30

Applicant: David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

Inventor： David Esseni ,  Luca Selmi ,  Roberto Bez ,  Alberto Modelli

IPC: H01L29788

CPC classification number: H01L29/66825 ,  G11C16/0416 ,  H01L27/11521 ,  H01L29/7885

Abstract: The memory cell is formed in a body of a P-type semiconductor material forming a channel region and housing N-type drain and source regions at two opposite sides of the channel region. A floating gate region extends above the channel region. A P-type charge injection region extends in the body contiguously to the drain region, at least in part between the channel region and the drain region. An N-type base region extends between the drain region, the charge injection region, and the channel region. The charge injection region and the drain region are biased by special contact regions so as to forward bias the PN junction formed by the charge injection region and the base region. The holes thus generated in the charge injection region are directly injected through the base region into the body, where they generate, by impact, electrons that are injected towards the floating gate region.

Abstract translation: 存储单元形成在形成沟道区域的P型半导体材料的主体中，并且在沟道区域的两个相对侧容纳N型漏极和源极区域。 浮动栅极区域在沟道区域的上方延伸。 P型电荷注入区域至少部分地在沟道区域和漏极区域之间在体内连续地延伸到漏极区域。 N型基极区域在漏极区域，电荷注入区域和沟道区域之间延伸。 电荷注入区域和漏极区域被特殊的接触区域偏置，以使由电荷注入区域和基极区域形成的PN结正向偏置。 这样在电荷注入区域中产生的孔直接通过基底区域注入到体内，在那里它们通过冲击产生被注入到浮动栅极区域的电子。

公开(公告)号：US5990526A

公开(公告)日：1999-11-23

申请号：US27343

申请日：1998-02-20

Applicant: Roberto Bez ,  Alberto Modelli

Inventor： Roberto Bez ,  Alberto Modelli

IPC: H01L21/8247 ,  H01L29/76 ,  H01L27/10 ,  H01L29/792 ,  H01L29/94

CPC classification number: H01L27/11519 ,  H01L27/11521

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over the second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over the second well in a second direction substantially orthogonal to the first direction and forming columns of memory cells, each strip of the second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over the second well in the second direction and intercalated to the strips of the second plurality, electrically contacting the second electrodes of the cells. A fourth plurality of strips of conductive material is provided extending over the second well in the second direction and intercalated to the strips of the second and the third pluralities, electrically contacting the second well in a succession of contact points distributed longitudinally to each strip of the fourth plurality.

Abstract translation: 一种存储器件，包括具有第一类型的掺杂剂的半导体材料衬底，在衬底中形成的具有第二类型的掺杂剂的第一半导体材料; 具有形成在第一阱中的第一类型的掺杂剂的第二半导体材料，形成在第二阱内的存储器单元的阵列。 每个存储单元包括分别由形成在第二阱中的第二类型的掺杂剂的第一和第二掺杂区域以及控制栅极电极分别形成的第一电极和第二电极。 所述存储器阵列包括在第一方向上在所述第二阱上延伸的第一多个导电材料条，并且形成行的存储器单元;第二多个导电材料条，沿第二方向在第二方向上延伸，所述第二方向基本上垂直于所述第一 方向和形成存储器单元的列，第二多个的每个条带电接触相应组的存储单元的第一电极;第三多个导电材料条，沿着第二方向在第二阱上延伸并插入到 所述第二多个电极与所述电池的第二电极电接触。 提供了第四多个导电材料条，其沿着第二方向在第二阱上延伸并且插入第二和第三多个的条带中，并且将第二阱的一系列接触点电连接到纵向分配到每个条带 第四个。

公开(公告)号：US6071778A

公开(公告)日：2000-06-06

申请号：US389955

申请日：1999-09-03

Applicant: Roberto Bez ,  Alberto Modelli

Inventor： Roberto Bez ,  Alberto Modelli

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type; a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in said first well; an array of memory cells formed within said second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in said second well, and a control gate electrode. The memory array comprises a first plurality of strips of conductive material extending over said second well in a first direction and forming rows of memory cells, a second plurality of strips of conductive material extending over said second well in a second direction substantially orthogonal to said first direction and forming columns of memory cells, each strip of said second plurality electrically contacting the first electrodes of a respective group of memory cells, a third plurality of strips of conductive material extending over said second well in said second direction and intercalated to the strips of the second plurality, electrically contacting the second electrodes of the cells. A fourth plurality of strips of conductive material is provided extending over said second well in said second direction and intercalated to the strips of said second and third pluralities, electrically contacting the second well in a succession of contact points distributed longitudinally to each strip of said fourth plurality.

Abstract translation: 一种存储器件，包括具有第一类型的掺杂剂的半导体材料衬底; 在衬底中形成有第二类型的掺杂剂的第一半导体材料; 具有形成在所述第一阱中的第一类型的掺杂剂的第二半导体材料; 形成在所述第二井内的一组存储单元。 每个存储单元包括分别由形成在所述第二阱中的第二类型掺杂剂的第一掺杂区域和第二掺杂区域形成的第一电极和第二电极以及控制栅电极。 所述存储器阵列包括在第一方向上在所述第二阱上延伸的第一多个导电材料条，并且形成行存储器单元;第二多个导电材料条，沿着与所述第一 方向和形成存储器单元的列，所述第二多个的每个条带电接触相应组的存储单元的第一电极;第三多个导电材料条，沿着所述第二方向在所述第二阱上延伸并插入到 所述第二多个电极与所述电池的第二电极电接触。 提供了第四多个导电材料条带，其在所述第二方向上在所述第二阱上延伸并且插入所述第二和第三多个的条带中，并且将所述第二阱的一系列接触点电连接到所述第四部分 复数。

公开(公告)号：US20110084247A1

公开(公告)日：2011-04-14

申请号：US12969652

申请日：2010-12-16

Applicant: Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

IPC: H01L45/00 ,  H01L27/082

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

Abstract translation: 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

公开(公告)号：US07606056B2

公开(公告)日：2009-10-20

申请号：US11317622

申请日：2005-12-22

Applicant: Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

IPC: G11C5/06

CPC classification number: H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

Abstract translation: 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。

公开(公告)号：US07227765B2

公开(公告)日：2007-06-05

申请号：US10970842

申请日：2004-10-20

Applicant: Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

Inventor： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

Abstract: A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

Abstract translation: 一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置 用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。 非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

公开(公告)号：US07110289B1

公开(公告)日：2006-09-19

申请号：US10816271

申请日：2004-03-31

Applicant: Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

Inventor： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

IPC: G11C11/15

CPC classification number: G11C11/15

Abstract: In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

Abstract translation: 在用于减少由磁存储器消耗的功率的方法和系统中，磁存储器单元耦合到位线并与多个数字线相关联。 位线中提供位线电流。 与位线电流基本相同的时刻，在数字线中并联提供数字电流。 数字和位线电流允许磁存储单元被并行写入多个状态。

公开(公告)号：US20060205136A1

公开(公告)日：2006-09-14

申请号：US11317679

申请日：2005-12-22

Applicant: Paolo Tessariol ,  Roberto Bez ,  Marcello Mariani

Inventor： Paolo Tessariol ,  Roberto Bez ,  Marcello Mariani

IPC: H01L21/8238

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.

公开(公告)号：US20050064606A1

公开(公告)日：2005-03-24

申请号：US10902508

申请日：2004-07-29

Applicant: Fabio Pellizzer ,  Roberto Bez

Inventor： Fabio Pellizzer ,  Roberto Bez

IPC: H01L27/24 ,  H01L21/00

CPC classification number: H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract translation: 一种制造相变存储器阵列的方法，包括以下步骤：形成以行和列排列的多个PCM单元; 以及形成用于连接布置在同一列上的PCM单元的多个电阻位线，每个电阻位线包括由相应的阻挡部分覆盖的各个相变材料部分。 在形成电阻位线之后，电阻位线的电连接结构直接形成为与电阻位线的势垒部分接触。

公开(公告)号：US20050062497A1

公开(公告)日：2005-03-24

申请号：US10948079

申请日：2004-09-23

Applicant: Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

Inventor： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

IPC: G11C16/02 ,  G11C16/04 ,  H03K3/037 ,  H03K19/177

CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

Abstract: The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

Abstract translation: 本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元 包括多个控制单元的布置。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值， 以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。