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    Hierarchical management for multiprocessor system with real-time attributes
    5.
    发明授权
    Hierarchical management for multiprocessor system with real-time attributes 失效
    具有实时属性的多处理器系统的分层管理

    公开(公告)号：US07299372B2

    公开(公告)日：2007-11-20

    申请号：US10912481

    申请日：2004-08-05

    申请人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  Michael Fan Wang

    发明人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  Michael Fan Wang

    IPC分类号： G06F1/28

    CPC分类号： G06F1/3203

    摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

    摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

    Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation
    6.
    发明授权
    Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
    具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法

    公开(公告)号：US07107363B2

    公开(公告)日：2006-09-12

    申请号：US10464882

    申请日：2003-06-19

    申请人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

    发明人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Takeshi Yamazaki

    IPC分类号： G06F3/00

    CPC分类号： G06F9/5011 ,  G06F2209/5014

    摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.

    摘要翻译： 本发明在一个方面公开了一种微处理器。 在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。 微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。 在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。 还公开了一种协调带宽分配的方法和处理器组件。

    Method of resource arbitration
    7.
    发明授权
    Method of resource arbitration 失效
    资源仲裁方法

    公开(公告)号：US07099975B2

    公开(公告)日：2006-08-29

    申请号：US10730952

    申请日：2003-12-09

    申请人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

    发明人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F13/3625

    摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

    摘要翻译： 一种改进的资源仲裁方法和装置。 定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器（ARC），通过该资源访问资源。 在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。 如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

    Methods and apparatus for reducing command processing latency while maintaining coherence
    9.
    发明授权
    Methods and apparatus for reducing command processing latency while maintaining coherence 失效
    减少命令处理延迟同时保持一致性的方法和装置

    公开(公告)号：US08112590B2

    公开(公告)日：2012-02-07

    申请号：US11846697

    申请日：2007-08-29

    申请人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Mark S. Fredrickson ,  Charles Ray Johns ,  David John Krolak

    发明人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Mark S. Fredrickson ,  Charles Ray Johns ,  David John Krolak

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F12/0804 ,  G06F12/0831

    摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。

    Dynamic data cache invalidate with data dependent expiration
    10.
    发明授权
    Dynamic data cache invalidate with data dependent expiration 有权
    动态数据缓存无效，与数据相关的到期

    公开(公告)号：US07836258B2

    公开(公告)日：2010-11-16

    申请号：US11559090

    申请日：2006-11-13

    申请人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich

    发明人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0875 ,  G06F12/0808 ,  G06F12/1045 ,  G06T1/60

    摘要： According to embodiments of the invention, a distributed time base signal may be coupled to a memory directory which provides address translation for data located within a memory cache. The memory directory may have attribute bits which indicate whether or not the memory entries have been accessed by the distributed time base signal. Furthermore, the memory directory may have attribute bits which indicate whether or not a memory directory entry should be considered invalid after an access to the memory entry by the distributed time base signal. If the memory directory entry has been accessed by the distributed time base signal and the memory directory entry should be considered invalid after the access by the time base signal, any attempted address translation using the memory directory entry may cause a cache miss. The cache miss may initiate the retrieval of valid data from memory.

    摘要翻译： 根据本发明的实施例，分布式时基信号可以耦合到为位于存储器高速缓存内的数据提供地址转换的存储器目录。 存储器目录可以具有指示存储器条目是否已经被分布式时基信号访问的属性位。 此外，存储器目录可以具有指示在通过分布式时基信号访问存储器条目之后存储目录条目是否应被视为无效的属性位。 如果通过分布式时基信号访问存储器目录条目，并且在通过时基信号访问之后，存储器目录条目应被视为无效，则使用存储器目录条目的任何尝试的地址转换可能导致高速缓存未命中。 高速缓存未命中可以启动从存储器检索有效数据。