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1.发明申请公开(公告)号：US20120102379A1
公开(公告)日：2012-04-26
申请号：US13031531
申请日：2011-02-21
CPC分类号： G06F11/1072 , G11C11/5621 , G11C11/5671
摘要： A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.
摘要翻译： 具有存储器的数据存储设备中的方法包括：接收要存储在存储器的单元组中的位值，并根据可调参数交织接收的位值以形成多个交错数据位组。 该方法还包括将多个交织的数据比特组写入该组小区。
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公开(公告)号：US20140029336A1
公开(公告)日：2014-01-30
申请号：US13599854
申请日：2012-08-30
申请人： ANAND VENKITACHALAM , SATEESH DESIREDDI , JAYAPRAKASH NARADASI , MANUEL ANTONIO D'ABREU , STEPHEN SKALA
发明人： ANAND VENKITACHALAM , SATEESH DESIREDDI , JAYAPRAKASH NARADASI , MANUEL ANTONIO D'ABREU , STEPHEN SKALA
CPC分类号： G11C16/349 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/28 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C29/021
摘要： A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment.
摘要翻译： 一种方法包括在包括非易失性存储器的数据存储设备中，将更新的参考电压选择为参考电压，第一替代参考电压和第二替代参考电压之一。 基于参考电压并基于电压增量来计算第一备用参考电压和第二备用参考电压。 更新的参考电压的选择基于错误计数的比较，每个错误计数与参考电压，第一替代参考电压和第二替代参考电压中唯一的一个相关联。 该方法包括将参考电压重置为更新的参考电压，将电压增量重新设置为小于电压增量的复位电压增量，以及基于复位参考电压并基于复位电压增量选择附加更新的参考电压 。
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3.发明授权公开(公告)号：US08560919B2
公开(公告)日：2013-10-15
申请号：US13031531
申请日：2011-02-21
IPC分类号： H03M13/00
CPC分类号： G06F11/1072 , G11C11/5621 , G11C11/5671
摘要： A method in a data storage device with a memory includes receiving bit values to be stored at a set of cells of the memory and interleaving the received bit values to form multiple interleaved groups of data bits according to an adjustable parameter. The method also includes writing the multiple interleaved groups of data bits to the set of cells.
摘要翻译： 具有存储器的数据存储设备中的方法包括：接收要存储在存储器的单元组中的位值，并根据可调参数交织接收的位值以形成多个交错数据位组。 该方法还包括将多个交织的数据比特组写入该组小区。
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公开(公告)号：US08392807B2
公开(公告)日：2013-03-05
申请号：US12882357
申请日：2010-09-15
IPC分类号： H03M13/00
CPC分类号： G06F11/1012 , H03M13/151 , H03M13/1545 , H03M13/1555 , H03M13/3723 , H03M13/6561 , H04L1/0061
摘要： Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation.
摘要翻译： 公开了执行分布式ECC操作的系统和方法。 一种方法包括在存储器装置的控制器中接收包括用于数据块的数据块和主纠错编码（ECC）数据的数据。 数据块包括数据的第一子块和对应于第一子块的第一ECC数据。 该方法包括启动数据块ECC操作以使用主ECC数据处理数据块，并启动子块ECC操作以使用第一ECC数据处理第一子块。 该方法还包括基于子块ECC操作的结果选择性地启动数据块ECC操作的错误位置搜索。
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5.发明授权Method and system for providing a codec clock signal at a desired operational rate 有权用于以期望的操作速率提供编解码器时钟信号的方法和系统公开(公告)号：US07224756B2
公开(公告)日：2007-05-29
申请号：US10144295
申请日：2002-05-13
IPC分类号： H04L27/08
摘要： A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.
摘要翻译： 公开了一种用于以期望的操作速率提供和操作具有时钟信号的代码的时钟发生器系统和方法。 时钟发生器系统还具有锁相环电路。 时钟发生器系统确定编解码器的电路环境内的可用时钟信号是否具有期望的时钟速率。 如果可用的时钟信号具有所需的时钟速率，则时钟发生器系统以可用的时钟信号提供和操作编解码器。 如果可用的时钟信号不具有期望的时钟速率，则锁相环电路从可用时钟信号产生具有所需时钟速率的期望时钟信号，并提供所需的时钟信号并且对编解码器进行操作。
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6.发明授权Analog to digital converters with integral sample rate conversion and systems and methods using the same 有权具有整体采样率转换的模数转换器及使用其的系统和方法公开(公告)号：US06608572B1
公开(公告)日：2003-08-19
申请号：US09944736
申请日：2001-08-31
IPC分类号： H03M700
CPC分类号： H03H17/0614
摘要： An integrated analog to digital and sample rate converter 206 includes sampling circuitry 207 for receiving an analog signal and generating a single or multibit stream of digital signals at a first rate. A leaky integrator filter 208 removes quantization noise from the stream of samples such that resampling can be carried out. Circuitry 209/210 resamples the filtered stream of samples output from leaky integrator filter 208 to generate an output stream of samples at a second rate.
摘要翻译： 集成的模数与采样速率转换器206包括用于接收模拟信号并以第一速率产生单个或多个数字信号流的采样电路207。 泄漏积分器滤波器208从样本流中去除量化噪声，使得可以执行重采样。 电路209/210对从泄漏积分器滤波器208输出的滤波后的样本流进行再取样，以生成第二速率的样本输出流。
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公开(公告)号：US07154562B1
公开(公告)日：2006-12-26
申请号：US10685128
申请日：2003-10-14
CPC分类号： H04N5/202
摘要： A method of gamma correction includes selecting lower and upper reference curves corresponding to selected reference gamma values. A gamma correction curve is generated from a corresponding gamma correction value and cross-correlated with the upper and lower reference curves to generate a corresponding set of cross-correlation factors. The set of cross-correlation factors are stored and indexed to the corresponding gamma value. An input value is received for gamma correction with the corresponding gamma value. Data from the upper and lower reference curves indexed by the input value are then operated one with the cross-correlation factors to generate a gamma corrected output value.
摘要翻译： 伽马校正的方法包括选择对应于所选参考伽马值的下参考曲线和上参考曲线。 从相应的伽马校正值产生伽马校正曲线，并与上参考曲线和下参考曲线交叉相关，以产生相应的一组互相关因子。 互相关因子的集合被存储并被索引到相应的伽马值。 接收用于具有相应伽马值的伽马校正的输入值。 然后，通过输入值索引的来自上下参考曲线的数据与互相关因子一起运算，以产生伽马校正输出值。
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8.发明授权Sample rate converters using virtual sample rates and analog to digital and digital to analog converters using the same 有权采样速率转换器采用虚拟采样率，模数转换器和数模转换器采用相同的采样率公开(公告)号：US06642863B1
公开(公告)日：2003-11-04
申请号：US10094978
申请日：2002-03-11
申请人： Anand Venkitachalam , Dylan Alexander Hester , Brian Frank Bounds , Rajendra Datar , Krishnan Subramoniam
发明人： Anand Venkitachalam , Dylan Alexander Hester , Brian Frank Bounds , Rajendra Datar , Krishnan Subramoniam
IPC分类号： H03M700
CPC分类号： H03H17/0628 , G11B20/10527 , H03H17/0642 , H03H17/0685
摘要： A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.
摘要翻译： 一种在数据转换器中执行采样速率转换的方法，该数据转换器是从对应于天然采样率和自然过采样因子的过采样时钟操作的。 选择虚拟采样率和虚拟过采样因子与本机采样率和原始过采样因子成比例。 具有数据采样率的数据流被虚拟过采样因子采样。 数据流也用接近于数据采样率与虚拟采样率的比率的重采样比进行重采样。
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9.发明授权公开(公告)号：US06489901B1
公开(公告)日：2002-12-03
申请号：US09944738
申请日：2001-08-31
IPC分类号： H03M704
CPC分类号： H03H17/0294
摘要： A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.
摘要翻译： 采样率转换器210,209包括用于响应于由时钟使能信号控制的时钟来处理数字数据的滤波器210，滤波器210以第一采样率接收数字数据并以第二采样率输出数字数据。 重采样器电路209产生具有接近第一采样率和第二采样率之间的比率的第一占空比的时钟使能信号的第一选定周期。 选择性地，生成具有第二占空比的选择的时钟使能信号的周期，以最小化在时钟使能信号的第一选定周期上累积的误差。
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公开(公告)号：US20120023384A1
公开(公告)日：2012-01-26
申请号：US12882357
申请日：2010-09-15
CPC分类号： G06F11/1012 , H03M13/151 , H03M13/1545 , H03M13/1555 , H03M13/3723 , H03M13/6561 , H04L1/0061
摘要： Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation.
摘要翻译： 公开了执行分布式ECC操作的系统和方法。 一种方法包括在存储器装置的控制器中接收包括用于数据块的数据块和主纠错编码（ECC）数据的数据。 数据块包括数据的第一子块和对应于第一子块的第一ECC数据。 该方法包括启动数据块ECC操作以使用主ECC数据处理数据块，并启动子块ECC操作以使用第一ECC数据处理第一子块。 该方法还包括基于子块ECC操作的结果选择性地启动数据块ECC操作的错误位置搜索。
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