公开(公告)号：US06642876B2

公开(公告)日：2003-11-04

申请号：US10206424

申请日：2002-07-26

Applicant: Krishnan Subramoniam ,  Jens Puchert ,  Brian K. Straup

Inventor： Krishnan Subramoniam ,  Jens Puchert ,  Brian K. Straup

IPC: H03H166

CPC classification number: H04H60/04 ,  G06F3/162

Abstract: A system and method of operating a codec in an operational mode are disclosed. The codec is operated in a digital centric mode. The digital centric mode involves the following: An analog mixer of the codec first mixes analog signals, if any, to produce a mixed analog signal. An analog-to-digital converter converts the mixed analog signal into a converted digital signal. A digital mixer mixes the converted digital signal with digital signals that are otherwise generally unavailable as analog signals to the codec without additional conversions to produce a mixed digital signal. A digital-to-analog converter converts the mixed digital signal into a mixed analog signal. A digital processor may perform digital effects processing on the mixed digital signal to add digital effects to the mixed digital signal. The codec is still able to alternatively operate in an analog centric mode, a host processing mode, or a multi-channel mode.

Abstract translation: 公开了一种在操作模式下操作编解码器的系统和方法。 编解码器以数字中心模式运行。 数字中心模式包括以下内容：编解码器的模拟混频器首先混合模拟信号（如果有的话）以产生混合模拟信号。 模数转换器将混合模拟信号转换成转换的数字信号。 数字混频器将转换的数字信号与数字信号混合，否则数字信号通常不能作为模拟信号提供给编解码器，而不需要额外的转换来产生混合数字信号。 数模转换器将混合数字信号转换为混合模拟信号。 数字处理器可以对混合数字信号执行数字效果处理，以将数字效果添加到混合数字信号。 编解码器仍然能够以模拟中心模式，主机处理模式或多通道模式操作。

公开(公告)号：US20060044468A1

公开(公告)日：2006-03-02

申请号：US11041582

申请日：2005-01-24

Applicant: Ahsan Chowdhury ,  James Antone ,  Krishnan Subramoniam

Inventor： Ahsan Chowdhury ,  James Antone ,  Krishnan Subramoniam

IPC: H04N11/00

CPC classification number: H04N5/44513 ,  H04N5/63 ,  H04N7/035 ,  H04N7/088

Abstract: A single-chip video decoder includes a primary data path for capturing and slicing vertical blanking interval information carried by a primary channel of video data received by a video decoder. Power control circuitry is operable during an inactive period of the video decoder to activate the primary data path during vertical blanking intervals of the received primary channel of video data for capturing and slicing the vertical blanking interval data; and to deactivate the primary data path between the vertical blanking interval and a subsequent vertical blanking interval of the received primary channel of video data to reduce power consumption. According to further inventive concepts, analog and/or digital circuitry which is unnecessary for capturing and slicing the vertical blanking information, including data paths processing secondary channels of video data, is deactivated during substantially the entire inactive period of the video decoder. In an additional embodiment, the input/output ports of the video decoder are set into a static state for substantially the entire inactive period.

Abstract translation: 单片视频解码器包括用于捕获和分割由视频解码器接收的视频数据的主要信道携带的垂直消隐间隔信息的主数据路径。 功率控制电路可在视频解码器的非活动时段期间操作，以便在所接收的视频数据主通道的垂直消隐间隔期间激活主要数据路径，用于捕捉和分割垂直消隐间隔数据; 并且停用垂直消隐间隔和所接收的视频数据的主要信道的随后的垂直消隐间隔之间的主数据路径，以减少功耗。 根据另外的发明概念，在视频解码器的基本上整个非活动时段期间，不需要用于捕获和分割垂直消隐信息（包括处理视频数据的次要信道的数据路径）的模拟和/或数字电路。 在另外的实施例中，视频解码器的输入/输出端口在大体上整个非活动期间被设置为静态。

公开(公告)号：US06542094B1

公开(公告)日：2003-04-01

申请号：US10090331

申请日：2002-03-04

Applicant: Anad Venkitachalam ,  Rajendra Datar ,  Krishnan Subramoniam

Inventor： Anad Venkitachalam ,  Rajendra Datar ,  Krishnan Subramoniam

IPC: H03M700

CPC classification number: H03H17/0614 ,  H03H17/0621

Abstract: A sample rate converter for converting a data stream having a first base sampling frequency to a data stream having a second base sampling frequency. Up-sampling circuitry receives first oversampled data having a first oversampling ratio with respects to the first base frequency and outputs second oversampled data having a second oversampling ratio with respects to the first base sampling frequency. Resampling circuitry resamples the second oversampled data by a resampling frequency ratio of integers representing a ratio of the first and second base frequencies and generates third oversampled data having the second oversampling ratio with respects to the second base frequency. Down-sampling circuitry then down-samples the third oversampled data and generates fourth oversampled data having the first oversampling ratio with respects to the second base frequency.

Abstract translation: 一种用于将具有第一基本采样频率的数据流转换为具有第二基本采样频率的数据流的采样率转换器。 上采样电路接收相对于第一基本频率具有第一过采样比率的第一过采样数据，并输出相对于第一基本采样频率具有第二过采样比的第二过采样数据。 重采样电路通过表示第一和第二基本频率的比率的整数的重采样频率比对第二过采样数据进行重采样，并且产生具有相对于第二基频的第二过采样比的第三过采样数据。 下采样电路然后对第三过采样数据进行下采样，并产生相对于第二基频的第一过采样数据。

公开(公告)号：US07224756B2

公开(公告)日：2007-05-29

申请号：US10144295

申请日：2002-05-13

Applicant: Krishnan Subramoniam ,  Jens Puchert ,  Anand Venkitachalam ,  Brian K. Straup ,  John L. Melanson

Inventor： Krishnan Subramoniam ,  Jens Puchert ,  Anand Venkitachalam ,  Brian K. Straup ,  John L. Melanson

IPC: H04L27/08

CPC classification number: G06F1/08 ,  H03L7/16 ,  H03L7/18

Abstract: A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.

Abstract translation: 公开了一种用于以期望的操作速率提供和操作具有时钟信号的代码的时钟发生器系统和方法。 时钟发生器系统还具有锁相环电路。 时钟发生器系统确定编解码器的电路环境内的可用时钟信号是否具有期望的时钟速率。 如果可用的时钟信号具有所需的时钟速率，则时钟发生器系统以可用的时钟信号提供和操作编解码器。 如果可用的时钟信号不具有期望的时钟速率，则锁相环电路从可用时钟信号产生具有所需时钟速率的期望时钟信号，并提供所需的时钟信号并且对编解码器进行操作。

公开(公告)号：US20060078054A1

公开(公告)日：2006-04-13

申请号：US10964547

申请日：2004-10-13

Applicant: Daniel Gudmundson ,  John Melanson ,  Rahul Singh ,  James Antone ,  Ahsan Chowdhury ,  Krishnan Subramoniam

Inventor： Daniel Gudmundson ,  John Melanson ,  Rahul Singh ,  James Antone ,  Ahsan Chowdhury ,  Krishnan Subramoniam

IPC: H04N11/02 ,  H04N11/04 ,  H04N7/12 ,  H04B1/66

CPC classification number: H04N5/4401 ,  H04N5/602 ,  H04N5/76 ,  H04N5/781 ,  H04N9/8042 ,  H04N11/20 ,  H04N21/4147 ,  H04N21/4305

Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Abstract translation: 视频解码器系统，其中模数转换器和复合解码器均由诸如晶体源的稳定采样时钟驱动。 复合解码器的输出被提供给源速率转换器，其具有提供给数字输出格式器的输出。 数字输出格式化器由输出时钟驱动，如果需要，可以将其锁定到源时钟。 输出时钟由时钟发生器开发，时钟发生器可以是几种不同类型之一，包括分数N个合成器，直接数字合成器或穿孔时钟。

公开(公告)号：US06608572B1

公开(公告)日：2003-08-19

申请号：US09944736

申请日：2001-08-31

Applicant: Anand Venkitachalam ,  Joe Welser ,  Manoj Soman ,  Krishnan Subramoniam

Inventor： Anand Venkitachalam ,  Joe Welser ,  Manoj Soman ,  Krishnan Subramoniam

IPC: H03M700

CPC classification number: H03H17/0614

Abstract: An integrated analog to digital and sample rate converter 206 includes sampling circuitry 207 for receiving an analog signal and generating a single or multibit stream of digital signals at a first rate. A leaky integrator filter 208 removes quantization noise from the stream of samples such that resampling can be carried out. Circuitry 209/210 resamples the filtered stream of samples output from leaky integrator filter 208 to generate an output stream of samples at a second rate.

Abstract translation: 集成的模数与采样速率转换器206包括用于接收模拟信号并以第一速率产生单个或多个数字信号流的采样电路207。 泄漏积分器滤波器208从样本流中去除量化噪声，使得可以执行重采样。 电路209/210对从泄漏积分器滤波器208输出的滤波后的样本流进行再取样，以生成第二速率的样本输出流。

公开(公告)号：US07339628B2

公开(公告)日：2008-03-04

申请号：US10964547

申请日：2004-10-13

Applicant: Daniel Gudmondson ,  John L. Melanson ,  Rahul Singh ,  James A. Antone ,  Ahsan Habib Chowdhury ,  Krishnan Subramoniam

Inventor： Daniel Gudmondson ,  John L. Melanson ,  Rahul Singh ,  James A. Antone ,  Ahsan Habib Chowdhury ,  Krishnan Subramoniam

IPC: H03M1/12

CPC classification number: H04N5/4401 ,  H04N5/602 ,  H04N5/76 ,  H04N5/781 ,  H04N9/8042 ,  H04N11/20 ,  H04N21/4147 ,  H04N21/4305

Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Abstract translation: 视频解码器系统，其中模数转换器和复合解码器均由诸如晶体源的稳定采样时钟驱动。 复合解码器的输出被提供给源速率转换器，其具有提供给数字输出格式器的输出。 数字输出格式化器由输出时钟驱动，如果需要，可以将其锁定到源时钟。 输出时钟由时钟发生器开发，时钟发生器可以是几种不同类型之一，包括分数N合成器，直接数字合成器或穿孔时钟。

公开(公告)号：US07162029B2

公开(公告)日：2007-01-09

申请号：US10447606

申请日：2003-05-29

Applicant: Manoj Soman ,  Krishnan Subramoniam ,  Hua Hong ,  Rajendra Datar ,  John Laurence Melanson

Inventor： Manoj Soman ,  Krishnan Subramoniam ,  Hua Hong ,  Rajendra Datar ,  John Laurence Melanson

IPC: H04M1/00 ,  H04M9/00

CPC classification number: H03M1/68 ,  H03M1/785

Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.

Abstract translation: 增益或输入音量控制器和方法包括具有多个R2R分支，分别耦合到R2R分支的开关的修改的R2R梯形网络和用于分别控制开关以控制并提供信号的总增益值的开关控制器。 开关控制器还包括用于将增益控制信号映射到开关的映射器，其中增益控制信号分别激活或去激活开关。 精细增益控制级提供整体增益值的精细增益控制。 粗调增益控制级耦合到微增益控制级。 粗增益控制级包括经修改的R2R梯形网络，并提供总增益值的粗增益控制。

公开(公告)号：US07019677B1

公开(公告)日：2006-03-28

申请号：US10936997

申请日：2004-09-08

Applicant: Manoj Shridhar Soman ,  Krishnan Subramoniam ,  Rajendra Datar

Inventor： Manoj Shridhar Soman ,  Krishnan Subramoniam ,  Rajendra Datar

IPC: H03M1/66

CPC classification number: H03M1/1047 ,  H03M1/1061 ,  H03M1/682 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: A current steering digital to analog converter includes a current source for selectively providing a selected amount of current to an output in response to input data. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.

Abstract translation: 电流转向数模转换器包括电流源，用于响应于输入数据选择性地向输出提供选定量的电流。 电流源包括选定数量的子电流源，用于选择性地将所选择的电流量的分数提供给输出。 补偿电流源各自为输出提供选定量的补偿电流。 补偿控制电路响应于输入数据，选择性地激活和去激活子电流源中的所选择的电流源和补偿电流源，以在输出端提供电流补偿。

公开(公告)号：US06642863B1

公开(公告)日：2003-11-04

申请号：US10094978

申请日：2002-03-11

Applicant: Anand Venkitachalam ,  Dylan Alexander Hester ,  Brian Frank Bounds ,  Rajendra Datar ,  Krishnan Subramoniam

Inventor： Anand Venkitachalam ,  Dylan Alexander Hester ,  Brian Frank Bounds ,  Rajendra Datar ,  Krishnan Subramoniam

IPC: H03M700

CPC classification number: H03H17/0628 ,  G11B20/10527 ,  H03H17/0642 ,  H03H17/0685

Abstract: A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.

Abstract translation: 一种在数据转换器中执行采样速率转换的方法，该数据转换器是从对应于天然采样率和自然过采样因子的过采样时钟操作的。 选择虚拟采样率和虚拟过采样因子与本机采样率和原始过采样因子成比例。 具有数据采样率的数据流被虚拟过采样因子采样。 数据流也用接近于数据采样率与虚拟采样率的比率的重采样比进行重采样。