公开(公告)号：US5786272A

公开(公告)日：1998-07-28

申请号：US423397

申请日：1995-04-18

申请人： Maria Santina Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

发明人： Maria Santina Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/963 ,  Y10S438/97 ,  Y10S438/974

摘要： A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

公开(公告)号：US20140146616A1

公开(公告)日：2014-05-29

申请号：US13687706

申请日：2012-11-28

申请人： Andrea Marmiroli ,  Daniele Vimercati

发明人： Andrea Marmiroli ,  Daniele Vimercati

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/26

摘要： Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between semiconductor circuits may be performed with a test current generator and test current measurement circuit, and adjusting a threshold voltage of a semiconductor component of at least one circuit until the difference between the circuits is at a desired difference may be performed with a program circuit.

摘要翻译： 显示和描述用于改善半导体电路之间的匹配的装置，电路和方法。 可以利用测试电流发生器和测试电流测量电路来测量半导体电路之间的匹配差异，并且可以执行至少一个电路的半导体部件的阈值电压，直到电路之间的差异处于期望的差异为止 与程序电路。

公开(公告)号：US5407861A

公开(公告)日：1995-04-18

申请号：US68139

申请日：1993-05-26

申请人： Maria S. Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

发明人： Maria S. Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/963 ,  Y10S438/97 ,  Y10S438/974

摘要： A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

摘要翻译： 一种插头接触方法，其中在接触孔被蚀刻之后，整体上沉积粘合层（例如Ti / TiN）和填充金属（例如钨）。 然后使用两级蚀刻：首先，相对于粘合层优先蚀刻填充金属，直到端点信号首先指示所述粘合层暴露。 在这个阶段没有使用过筛。 此后，使用非优选蚀刻来清除填充金属的残留物，同时也均匀地降低粘附层的高度。 这防止了接触孔中的插塞的顶部凹陷。 然后将铝（或其他金属）沉积并图案化（使用叠层蚀刻以除去粘附层的不希望的部分），以实现所需的布线图案。 因此，在具有高纵横比接触的过程中，该过程减少了空隙以及所得到的金属化缺陷。 另外，残留粘附层有助于减少电迁移。