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9 条记录 (耗时 0.014 秒)

    Method of fabricating flat FED screens
    1.
    发明授权
    Method of fabricating flat FED screens 失效
    平面FED屏幕的制作方法

    公开(公告)号：US6036566A

    公开(公告)日：2000-03-14

    申请号：US942477

    申请日：1997-10-02

    申请人： Livio Baldi ,  Maria Santina Marangon

    发明人： Livio Baldi ,  Maria Santina Marangon

    IPC分类号： H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12 ,  H01L29/66

    CPC分类号： H01J9/025 ,  H01J1/3042

    摘要： The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

    摘要翻译： 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端是管状的并且具有小的曲率半径的部分。 微尖端通过在将阴极连接层与栅格层分隔开的电介质层中形成开口，沉积导电材料层以覆盖开口的壁而获得，并各向异性地蚀刻导电材料层以形成具有发射的向内倾斜表面 提示。 随后，去除围绕微尖头的电介质层的部分。

    Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof
    2.
    发明授权
    Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof 有权
    集成电阻器，包括该电阻器的相变存储元件及其制造方法

    公开(公告)号：US06946673B2

    公开(公告)日：2005-09-20

    申请号：US10345129

    申请日：2003-01-14

    申请人： Romina Zonca ,  Maria Santina Marangon ,  Giorgio De Santi

    发明人： Romina Zonca ,  Maria Santina Marangon ,  Giorgio De Santi

    IPC分类号： H01L45/00 ,  H01L47/00 ,  H01L29/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

    摘要翻译： 垂直电流阻力元件包括具有第一部分和第二部分的整体区域，第一部分和第二部分彼此顶部布置并由单一材料形成。 第一部分具有第一电阻率，第二部分具有低于第一电阻率的第二电阻率。 为此目的，首先形成具有均匀的电阻率和高于其它尺寸中的至少一个的高度的整体区域; 那么通过从顶部引入与整体区域的导电材料形成普遍共价键的物质来增加第一部分的电阻率，使得所述物质的浓度在第一部分中比在第二部分中更高 。 优选地，导电材料是选自TiAl，TiSi，TiSi 2，Ta，WSi的二元或三元合金，并且通过氮化获得电阻率的增加。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured
    5.
    发明授权
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured 有权
    因此制造Cu-damascene技术和相变存储器阵列中的相变存储器阵列的制造方法

    公开(公告)号：US07606056B2

    公开(公告)日：2009-10-20

    申请号：US11317622

    申请日：2005-12-22

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

    IPC分类号： G11C5/06

    CPC分类号： H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

    摘要翻译： 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。

    Method of fabricating flat fed screens, and flat screen obtained thereby
    6.
    发明授权
    Method of fabricating flat fed screens, and flat screen obtained thereby 有权
    制造扁平进给筛网的方法和由此得到的平面筛网

    公开(公告)号：US06465950B1

    公开(公告)日：2002-10-15

    申请号：US09482244

    申请日：2000-01-13

    申请人： Livio Baldi ,  Maria Santina Marangon

    发明人： Livio Baldi ,  Maria Santina Marangon

    IPC分类号： H01J6302

    CPC分类号： H01J9/025 ,  H01J1/3042

    摘要： The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.

    摘要翻译： 限定平面FED屏幕的阴极并且面对屏幕的栅格的电荷发射材料的微尖端是管状的并且具有小的曲率半径的部分。 微尖端通过在将阴极连接层与栅格层分隔开的电介质层中形成开口，沉积导电材料层以覆盖开口的壁而获得，并各向异性地蚀刻导电材料层以形成具有发射的向内倾斜表面 提示。 随后，去除围绕微尖头的电介质层的部分。

    Metallization over tungsten plugs
    7.
    发明授权
    Metallization over tungsten plugs 失效

    公开(公告)号：US5786272A

    公开(公告)日：1998-07-28

    申请号：US423397

    申请日：1995-04-18

    申请人： Maria Santina Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

    发明人： Maria Santina Marangon ,  Andrea Marmiroli ,  Giorgio Desanti

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/963 ,  Y10S438/97 ,  Y10S438/974

    摘要： A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

    Process for manufacturing integrated circuits formed on a semiconductor substrate and comprising tungsten layers
    9.
    发明申请
    Process for manufacturing integrated circuits formed on a semiconductor substrate and comprising tungsten layers 审中-公开
    用于制造形成在半导体衬底上并且包括钨层的集成电路的工艺

    公开(公告)号：US20080217776A1

    公开(公告)日：2008-09-11

    申请号：US12074776

    申请日：2008-03-05

    申请人： Maria Santina Marangon ,  Davide Erbetta

    发明人： Maria Santina Marangon ,  Davide Erbetta

    IPC分类号： H01L21/768 ,  H01L23/538

    CPC分类号： H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877

    摘要： An embodiment is described for manufacturing integrated circuits formed on a semiconductor substrate, which embodiment comprises forming a cobalt suicide layer on said semiconductor substrate, forming a layer comprising tungsten on said silicide layer, said cobalt suicide layer forming a barrier against the migration of the silicon atoms of said semiconductor substrate during the formation step of said layer comprising tungsten. An embodiment is also described for manufacturing contacts comprising tungsten of an integrated circuit formed on a semiconductor substrate.

    摘要翻译： 描述了用于制造形成在半导体衬底上的集成电路的实施例，该实施例包括在所述半导体衬底上形成硅化硅层，在所述硅化物层上形成包含钨的层，所述硅化钴层形成阻挡硅迁移的阻挡层 在包含钨的所述层的形成步骤期间所述半导体衬底的原子。 还描述了用于制造包括形成在半导体衬底上的集成电路的钨的触点的实施例。