公开(公告)号：US08829588B2

公开(公告)日：2014-09-09

申请号：US13191223

申请日：2011-07-26

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/788 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/513 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/7881

摘要： Embodiments relate to a nonvolatile memory (“NVM”) bitcell with a replacement metal control gate and an additional floating gate. The bitcell may be created using a standard complementary metal-oxide-semiconductor manufacturing processes (“CMOS processes”) without any additional process steps, thereby reducing the cost and time associated with fabricating a semiconductor device incorporating the NVM bitcell.

摘要翻译： 实施例涉及具有替换金属控制栅极和附加浮动栅极的非易失性存储器（“NVM”）位单元。 可以使用标准互补金属氧化物半导体制造工艺（“CMOS工艺”）而不需要任何额外的工艺步骤来产生位单元，从而降低与组装NVM位单元的半导体器件制造相关的成本和时间。

公开(公告)号：US08194468B2

公开(公告)日：2012-06-05

申请号：US13158002

申请日：2011-06-10

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5621 ,  G11C16/0441 ,  G11C16/10

摘要： A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read transistor.The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.

摘要翻译： 非易失性存储器（NVM）单元和编程方法，其中单元可以表示至少两个逻辑电平（例如，0和1），并且包括具有浮置栅极和带对带隧穿装置的读晶体管 （BTBT器件）与读取晶体管共享浮动栅极。 BTBT装置被配置为当BTBT装置被偏置使得其被积累时将第一电荷注入到浮动栅上的注入装置，以设置至少一个逻辑电平。

公开(公告)号：US20090170260A1

公开(公告)日：2009-07-02

申请号：US12403333

申请日：2009-03-12

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L21/8239

CPC分类号： G11C16/12

摘要： Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described.

摘要翻译： 电子电路被描述为具有位于电浮置栅极和半导体衬底之间的第一栅极电介质的第一晶体管。 第一注入电流流过第一栅极电介质以在栅电极上建立第一量的电荷。 电子电路还包括具有位于栅电极和半导体衬底之间的第二栅极电介质的第二晶体管。 带间隧穿电流在第二晶体管的价带和导带之间流动，以产生流过第二栅极电介质的第二注入电流，以在栅电极上建立第一量的电荷。 还描述了具有上述电路的非易失性存储单元电路。

公开(公告)号：US07456439B1

公开(公告)日：2008-11-25

申请号：US10884337

申请日：2004-07-01

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/74

CPC分类号： H01L29/0657 ,  G11C11/39 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/763 ,  H01L27/0617 ,  H01L27/0817 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/66363 ,  H01L29/74

摘要： A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.

摘要翻译： 半导体器件可以包括多个存储单元。 存储单元可以包括晶闸管，其至少一部分形成在半导体材料的柱中。 支柱可以包括限定第一直径的圆柱形圆周的侧壁。 在特定实施例中，与多个存储器单元相关联的支柱可以定义阵列的行和列。 在另一实施例中，柱可以相对于其行内的相邻支柱间隔第一距离直到第一直径。 在另外的另外的实施例中，柱可以相对于其柱内的相邻柱而间隔第二距离，该距离的幅度高达第一直径的两倍。

公开(公告)号：US07400255B2

公开(公告)日：2008-07-15

申请号：US11069515

申请日：2005-02-28

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： G08B13/14

CPC分类号： B07C5/344 ,  G01R31/01 ,  G01R31/2822 ,  H01L2223/6677 ,  Y10T29/49004

摘要： Wirelessly testing an RFID tag before it is packaged or otherwise entered into a process reserved for “working” RFID tags is described. Various processes that employ such wireless testing as well as various “on-die” RFID tag antenna designs for facilitating the wireless testing are also described.

摘要翻译： 在将RFID标签封装或以其他方式输入到为“工作”RFID标签保留的过程中进行无线测试时，将进行描述。 还描述了采用这种无线测试的各种过程以及用于促进无线测试的各种“裸片”RFID标签天线设计。

公开(公告)号：US07256430B1

公开(公告)日：2007-08-14

申请号：US11303228

申请日：2005-12-15

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/74

CPC分类号： H01L29/7408 ,  H01L29/7436

摘要： A thyristor memory device may comprise a capacitor electrode formed over a base region of the thyristor using a replacement gate process. During formation of the thyristor, a base-emitter boundary may be aligned relative to a shoulder of the capacitor electrode. In a particular embodiment, the replacement gate process may comprise defining a trench in a layer of dielectric over semiconductor material. Conductive material for the electrode may be formed over the dielectric and in the trench. It may further be patterned to form a shoulder for the electrode that extends over regions of the dielectric over a base region for the thyristor. The extent of the shoulder may be used to pattern the dielectric and/or to assist alignment of implants for the base and emitter regions of the thyristor.

摘要翻译： 晶闸管存储器件可以包括使用替换栅极工艺在晶闸管的基极区域上形成的电容器电极。 在晶闸管的形成期间，基极 - 发射极边界可以相对于电容器电极的台肩对准。 在特定实施例中，替换栅极工艺可以包括在半导体材料上的介电层中限定沟槽。 用于电极的导电材料可以形成在电介质和沟槽中。 可以进一步图案化以形成电极的肩部，该电极在用于晶闸管的基极区域上的电介质的区域上延伸。 可以使用肩部的程度来图案化电介质和/或辅助晶闸管的基极和发射极区域的植入物的对准。

公开(公告)号：US08598642B2

公开(公告)日：2013-12-03

申请号：US13027048

申请日：2011-02-14

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L21/02

CPC分类号： G11C16/10 ,  G06F17/5068 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7885

摘要： An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

摘要翻译： 描述了非对称非易失性存储器位单元。 位单元包括源极和漏极区域，其包括相同导电类型的载流子。 浮动栅极位于阱的顶部，并且在沟道区域以及源极和漏极区域的至少一部分上延伸。 漏极区域包括具有第二导电类型的附加载体，允许频带带通隧道。 源极区域包括第一导电类型的附加载流子，从而增加源极 - 栅极电容。 因此，位单元集成了选择装置，从而减小了位单元的整体尺寸。 可以在没有任何额外的CMOS工艺步骤的情况下创建位单元，或者通过添加单个额外的掩模步骤来创建位单元。

公开(公告)号：US08501562B1

公开(公告)日：2013-08-06

申请号：US12717966

申请日：2010-03-05

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/28273 ,  H01L21/76224 ,  H01L27/11206 ,  H01L29/66825

摘要： An example of a method of fabricating a gate oxide of a floating gate transistor includes forming a plurality of shallow trench isolation (STI) regions in a silicon wafer. The method also includes selectively filling the STI regions with oxide. Further, the method includes forming sacrificial oxide regions on the silicon wafer. Furthermore, the method includes forming implant regions in the silicon wafer. In addition, the method includes selectively removing the sacrificial oxide regions. The method further includes forming the gate oxide.

摘要翻译： 制造浮栅晶体管的栅极氧化物的方法的实例包括在硅晶片中形成多个浅沟槽隔离（STI）区域。 该方法还包括用氧化物选择性填充STI区域。 此外，该方法包括在硅晶片上形成牺牲氧化物区域。 此外，该方法包括在硅晶片中形成注入区域。 此外，该方法包括选择性地去除牺牲氧化物区域。 该方法还包括形成栅极氧化物。

公开(公告)号：US20130193501A1

公开(公告)日：2013-08-01

申请号：US13361801

申请日：2012-01-30

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7885

摘要： A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

摘要翻译： 具有一个或多个有源区的非易失性存储器（“NVM”）位单元，其电容耦合到浮置栅极，但是与源极和漏极分离。 从源极和漏极分离的电容器的包含允许改善对浮动栅极的电压的控制。 这反过来允许以比现有的比特单元更高的效率执行CHEI（或IHEI），从而需要电荷泵来向比特单元提供电流，最终减小比特单元的总大小。 比特单元可以成对地构造，进一步减少了每个比特单元的空间要求，从而减轻了单独电容器的空间要求。 位元还可以由CHEI（或IHEI）和BTBT单独操作，具体取决于在源极，漏极和电容/ s上施加的电压。

公开(公告)号：US20120205734A1

公开(公告)日：2012-08-16

申请号：US13027048

申请日：2011-02-14

申请人： Andrew E. Horch

发明人： Andrew E. Horch

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： G11C16/10 ,  G06F17/5068 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7885

摘要： An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

摘要翻译： 描述了非对称非易失性存储器位单元。 位单元包括源极和漏极区域，其包括相同导电类型的载流子。 浮动栅极位于阱的顶部，并且在沟道区域以及源极和漏极区域的至少一部分上延伸。 漏极区域包括具有第二导电类型的附加载体，允许频带带通隧道。 源极区域包括第一导电类型的附加载流子，从而增加源极 - 栅极电容。 因此，位单元集成了选择装置，从而减小了位单元的整体尺寸。 可以在没有任何额外的CMOS工艺步骤的情况下创建位单元，或者通过添加单个额外的掩模步骤来创建位单元。