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22 条记录 (耗时 0.016 秒)

    Power delivery noise cancellation mechanism
    1.
    发明授权
    Power delivery noise cancellation mechanism 失效
    电力输送噪声消除机制

    公开(公告)号：US07109755B2

    公开(公告)日：2006-09-19

    申请号：US10974220

    申请日：2004-10-27

    申请人： Dmitriy S. Garmatyuk ,  Christopher D. Loental ,  Andrew Martwick

    发明人： Dmitriy S. Garmatyuk ,  Christopher D. Loental ,  Andrew Martwick

    IPC分类号： H03K19/0175

    CPC分类号： H04L25/028 ,  H03K17/162

    摘要： An integrated circuit is disclosed. The integrated circuit includes a power delivery network (PDN), a first voltage rail coupled to the PDN, an input/output (I/O) buffer coupled to the first voltage rail and a driver coupled to the I/O buffer. The driver transmits a current waveform to the I/O buffer whenever a switching event occurs at the I/O buffer.

    摘要翻译： 公开了一种集成电路。 集成电路包括电力输送网络（PDN），耦合到PDN的第一电压轨，耦合到第一电压轨的输入/输出（I / O）缓冲器和耦合到I / O缓冲器的驱动器。 每当I / O缓冲区发生切换事件时，驱动程序将电流波形发送到I / O缓冲区。

    System for managing input/output address accesses at a bridge/memory controller
    3.
    发明授权
    System for managing input/output address accesses at a bridge/memory controller 失效
    用于管理桥/存储器控制器处的输入/输出地址访问的系统

    公开(公告)号：US6145030A

    公开(公告)日：2000-11-07

    申请号：US49829

    申请日：1998-03-27

    申请人： Andrew Martwick

    发明人： Andrew Martwick

    IPC分类号： G06F12/08 ,  G06F13/24 ,  G06F12/10 ,  G06F13/10 ,  G06F13/12 ,  G06F13/14

    CPC分类号： G06F13/24 ,  G06F12/0866

    摘要： An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

    摘要翻译： 一种装置，包括：输入/输出（I / O）地址验证单元，确定从处理器接收到的I / O地址是否被保护。 中断发生器耦合到I / O地址验证单元。 如果I / O地址被保护，中断发生器将产生一个中断。 中断记录器耦合到地址验证单元。 中断记录器记录中断的原因。

    Autodetection of a PCI express device operating at a wireless RF mitigation frequency
    6.
    发明申请
    Autodetection of a PCI express device operating at a wireless RF mitigation frequency 有权
    自动检测以无线RF减轻频率工作的PCI Express设备

    公开(公告)号：US20060143338A1

    公开(公告)日：2006-06-29

    申请号：US11026968

    申请日：2004-12-29

    申请人： Mikal Hunsaker ,  Karthi Vadivelu ,  Andrew Martwick

    发明人： Mikal Hunsaker ,  Karthi Vadivelu ,  Andrew Martwick

    IPC分类号： G06F3/06

    CPC分类号： G06F13/4295 ,  G06F2213/0026 ,  H04L7/10

    摘要： A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

    摘要翻译： 描述了检测符合PCI Express的端点设备的计算机系统。 具体地，计算机系统以第一频率对发射和接收电路进行计时，并启动训练序列。 如果端点设备以第一个频率成功列车，则端点设备符合PCI Express标准。 否则，计算机系统以第二频率发起另一训练序列。

    Asynchronous coupling and decoupling of chips
    7.
    发明授权
    Asynchronous coupling and decoupling of chips 有权

    公开(公告)号：US06906549B2

    公开(公告)日：2005-06-14

    申请号：US10334735

    申请日：2002-12-31

    申请人： Theodore Zale Schoenborn ,  Andrew Martwick

    发明人： Theodore Zale Schoenborn ,  Andrew Martwick

    IPC分类号： H04L25/45 ,  H03K17/16

    CPC分类号： H04L25/45

    摘要： In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

    System for managing input/output accesses at a bridge/memory controller having a status register for recording cause of interrupt
    9.
    发明授权
    System for managing input/output accesses at a bridge/memory controller having a status register for recording cause of interrupt 有权
    用于管理具有用于记录中断原因的状态寄存器的桥/存储器控制器的输入/输出存取的系统

    公开(公告)号：US06298399B1

    公开(公告)日：2001-10-02

    申请号：US09495500

    申请日：2000-01-31

    申请人： Andrew Martwick

    发明人： Andrew Martwick

    IPC分类号： G06F1324

    CPC分类号： G06F13/24 ,  G06F12/0866

    摘要： An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

    摘要翻译： 一种装置，包括：输入/输出（I / O）地址验证单元，确定从处理器接收到的I / O地址是否被保护。 中断发生器耦合到I / O地址验证单元。 如果I / O地址被保护，中断发生器将产生一个中断。 中断记录器耦合到地址验证单元。 中断记录器记录中断的原因。