Asynchronous coupling and decoupling of chips

    公开(公告)号:US06906549B2

    公开(公告)日:2005-06-14

    申请号:US10334735

    申请日:2002-12-31

    IPC分类号: H04L25/45 H03K17/16

    CPC分类号: H04L25/45

    摘要: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

    Generating and recovering clock signals based on differential scheme
    2.
    发明授权
    Generating and recovering clock signals based on differential scheme 有权
    基于差分方案生成和恢复时钟信号

    公开(公告)号:US06968474B2

    公开(公告)日:2005-11-22

    申请号:US10307307

    申请日:2002-12-02

    IPC分类号: G06F1/10 H04L7/00 G06F1/04

    CPC分类号: G06F1/10 H04L7/0008

    摘要: A method for recovering a clock signal communicated on a system bus. The method includes receiving at a receiver a first signal having a first polarity and receiving at the receiver a second signal having an opposite polarity to the first signal. The method also includes generating at the receiver a first clock signal based upon the first signal and the second signal.

    摘要翻译: 一种用于恢复在系统总线上传送的时钟信号的方法。 该方法包括在接收机处接收具有第一极性的第一信号,并在接收器处接收与第一信号具有相反极性的第二信号。 该方法还包括在接收器处基于第一信号和第二信号产生第一时钟信号。

    Current sharing in memory packages

    公开(公告)号:US06628528B2

    公开(公告)日:2003-09-30

    申请号:US09727989

    申请日:2000-11-30

    IPC分类号: H05K111

    摘要: A method including routing a signal from a memory device on an integrated circuit in a package to a memory module, and returning the signal to a reference line in the package between the memory module and the integrated circuit. Also, a method including providing a memory module including at least one memory package configured for electrically coupling to a bus on a system board, the at least one memory package comprising an integrated circuit including a plurality of memory devices, and a package substrate including a surface having a plurality of externally accessible contact points coupled to the memory devices and an externally accessible reference signal line and a surface of the package, and tuning the electrical characteristics of the memory package using an electrical potential between the contact points and the reference signal line.

    Differential clocking for digital platforms
    7.
    发明授权
    Differential clocking for digital platforms 有权
    数字平台的差分时钟

    公开(公告)号:US06510526B1

    公开(公告)日:2003-01-21

    申请号:US09471307

    申请日:1999-12-23

    IPC分类号: G06F104

    CPC分类号: G06F1/10 H04L7/0008

    摘要: A method for recovering a clock signal communicated on a system bus. The method includes receiving at a receiver a first signal having a first polarity and receiving at the receiver a second signal having an opposite polarity to the first signal. The method also includes generating at the receiver a first clock signal based upon the first signal and the second signal.

    摘要翻译: 一种用于恢复在系统总线上传送的时钟信号的方法。 该方法包括在接收机处接收具有第一极性的第一信号,并在接收器处接收与第一信号具有相反极性的第二信号。 该方法还包括在接收器处基于第一信号和第二信号产生第一时钟信号。