公开(公告)号：US4446518A

公开(公告)日：1984-05-01

申请号：US319811

申请日：1981-11-09

申请人： Angelo Casamatta

发明人： Angelo Casamatta

IPC分类号： G06F9/22 ,  G06F9/26

CPC分类号： G06F9/264

摘要： A microprogrammed control unit with multiple branch capability comprises in addition to a control memory, a first auxiliary read/write memory (21) having low parallelism and a second auxiliary read/write memory (30) having high parallelism. The reading of a microinstruction from the control memory also causes the reading of an information from the first auxiliary memory, such information being used to address the reading of the second auxiliary memory. The information read out from the second auxiliary memory specifies jump conditions (JC1, JC2, JC3) to be examined and jump addresses (JA1, JA2, JA3) and extends the information contained in the microinstruction read out from control memory.Thus it is possible to associate jump (or branch) microinstructions to operative microinstructions and particularly multiple branch microinstructions to curtail the design time of the microprogram and the control memory size devoted to store them.A priority network 40 coupled to the second auxiliary memory determines the priority to be followed during the concurrent examination of several jump conditions and selects the jump address among several possible addresses according to the highest priority verified jump condition.

摘要翻译： 具有多个分支能力的微程序控制单元除了具有低并行性的第一辅助读/写存储器（21）和具有高并行性的第二辅助读/写存储器（30）之外，还包括控制存储器。 从控制存储器读取微指令还导致从第一辅助存储器读取信息，这样的信息用于解决第二辅助存储器的读取。 从第二辅助存储器读出的信息指定要检查的跳转条件（JC1，JC2，JC3）和跳转地址（JA1，JA2，JA3），并且扩展从控制存储器读出的微指令中包含的信息。 因此，可以将跳转（或分支）微指令与操作微指令相关联，特别是多分支微指令，以缩短微程序的设计时间和专门用于存储微控制器的控制存储器大小。 耦合到第二辅助存储器的优先级网络40确定在并行检查几个跳转条件期间要遵循的优先级，并且根据最高优先级验证的跳转条件在若干可能地址中选择跳转地址。

公开(公告)号：US06173383B2

公开(公告)日：2001-01-09

申请号：US09102845

申请日：1998-06-23

申请人： Angelo Casamatta

发明人： Angelo Casamatta

IPC分类号： G06F1300

CPC分类号： G06F13/404

摘要： Interface bridge (13) between a system bus (ASBUS) and at least one local bus (11, 12), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (17, 18, 19) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (20, 21) and capable of addressing the entire system space.

摘要翻译： 在系统总线（ASBUS）与至少一个局部总线（11,12）之间的接口桥（13），可通过所述系统总线直接寻址的系统空间大于可通过本地总线直接寻址的系统空间，包括多个 可编程解码器（17,18,19），其中每个定义在通过本地总线直接寻址的范围内的不同范围，以及作为要转换或直接传送到系统总线的局部总线地址范围的范围属性，以及 将本地总线地址标识为包括在该范围内或其他范围内，使得根据本地总线地址是否属于其中一个范围以及在范围属性上，本地总线地址作为直接传送到系统总线 地址或由翻译逻辑（20,21）翻译并能够解决整个系统空间的地址。

公开(公告)号：US4279033A

公开(公告)日：1981-07-14

申请号：US23050

申请日：1979-03-22

申请人： Romeo Brunelli ,  Angelo Casamatta

发明人： Romeo Brunelli ,  Angelo Casamatta

IPC分类号： G06F13/18 ,  G06F13/42 ,  H04L5/14 ,  H04L5/16 ,  H04L29/08

CPC分类号： H04L5/1415 ,  G06F13/18 ,  G06F13/4269

摘要： A circuit for coupling together for bidirectional information communication pairs of devices of a digital data processing system, wherein such communication is effected by interlocked information signals, and wherein there is provided a single lead for the bidirectional transfer of such interlocked signals.

摘要翻译： 一种用于耦合到数字数据处理系统的双向信息通信对设备的电路，其中这种通信由互锁信息信号实现，并且其中提供了用于双向传送这种互锁信号的单个引线。

公开(公告)号：US5247629A

公开(公告)日：1993-09-21

申请号：US469870

申请日：1990-01-24

申请人： Angelo Casamatta ,  Calogero Mantellina ,  Daniele Zanzottera

发明人： Angelo Casamatta ,  Calogero Mantellina ,  Daniele Zanzottera

IPC分类号： G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F12/0284 ,  G06F12/0692 ,  G06F12/1027

摘要： In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses into addresses conventionally defined as real, the translation being performed by a first translation unit associated with and managed by the processor which generates the global data. The first translation is followed by the translation of the real address into a physical address generally differing for each local memory and performed by a plurality of translation units, each associated with one of the local memories and managed by the processor associated with that local memory.

公开(公告)号：US06243794B1

公开(公告)日：2001-06-05

申请号：US09006008

申请日：1998-01-12

申请人： Angelo Casamatta

发明人： Angelo Casamatta

IPC分类号： G06F1208

CPC分类号： G06F12/0813 ,  G06F2212/2542

摘要： A data-processing system with cc-NUMA architecture including a plurality of nodes each constituted by at least one processor intercommunicating with a DRAM-technology local memory using a local bus, the nodes intercommunicating using remote interface bridges and at least one intercommunication ring. The at least one processor has access to a system memory space defined by memory addresses. Each node includes a unit for configuring the local memory, for uniquely mapping a first portion of the system memory space, which is different for each node, onto a portion of the local memory and for mapping the portion of the system memory space which as a whole is uniquely mapped onto a portion of the local memory of all the other nodes onto the remaining portion of the local memory, and a SRAM-technology memory for storing labels with associated with a block of data stored in the remaining portion of local memory and each comprising an index identifying the block and bits indicating a coherence state of the block so that the remaining portion of local memory in each node constitutes a remote cache of the node.

摘要翻译： 一种具有cc-NUMA架构的数据处理系统，包括多个节点，每个节点由至少一个处理器使用本地总线与DRAM技术本地存储器相互通信，所述节点使用远程接口桥和至少一个互通环互通。 至少一个处理器可以访问由存储器地址定义的系统存储器空间。 每个节点包括用于配置本地存储器的单元，用于将对于每个节点不同的系统存储器空间的第一部分唯一地映射到本地存储器的一部分上，并且将系统存储器空间的部分映射为 整体被唯一映射到所有其他节点的本地存储器的一部分到本地存储器的剩余部分上，以及SRAM技术存储器，用于存储与存储在本地存储器的剩余部分中的数据块相关联的标签，以及 每个包括标识块的索引和指示块的相干状态的比特，使得每个节点中的本地存储器的剩余部分构成节点的远程高速缓存。

公开(公告)号：US5214776A

公开(公告)日：1993-05-25

申请号：US423820

申请日：1989-10-18

申请人： Carlo Bagnoli ,  Angelo Casamatta ,  Angelo Lazzari

发明人： Carlo Bagnoli ,  Angelo Casamatta ,  Angelo Lazzari

IPC分类号： G06F15/16 ,  G06F15/167

CPC分类号： G06F15/161 ,  G06F15/167

摘要： A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs), where consistency of the global data in each of the local memories is provided by a global write procedure according to which an agent CPUZ, willing to modify a global data in its own local memory, issues a write command on the system bus for performing the write operation in the local memory of another destination CPU of the system and characterizes the write command as a global write, so that all the CPUs connected to the system bus (including CPUZ) detect such command, perform such write operation in their related local memory and provide the destination CPU with a signal indicative of a performed write operation, so that the destination CPU, as "replier", may signal to CPUZ the successful execution of the global write. By this procedure, it is possible to use standard, commercially available system bus and interface circuits which require, for correct execution of the system bus protocol, the activation of both an "agent" or requesting processor and a "replier" or destination processor.

公开(公告)号：US4630041A

公开(公告)日：1986-12-16

申请号：US569127

申请日：1984-01-09

申请人： Angelo Casamatta ,  Walter Fossati

发明人： Angelo Casamatta ,  Walter Fossati

IPC分类号： G06F13/26 ,  H04Q1/00 ,  G06F3/04

CPC分类号： G06F13/26

摘要： Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11,12). The priority network directly receives on its input terminals the asynchronous interrupt signals and provides on its output terminals a binary code corresponding to the highest priority interrupt present on its input terminals. The interrupt code is latched in the register and is present on its output terminals. The code latched in the register is used by a validation circuit as a selection code of the related input interrupt signal. If such a signal is present, the code is validated, i.e., it is transferred to the central unit of the system. If the selected interrupt signal is not present, the code is not validated.

摘要翻译： 数据处理系统中的中断控制装置，用于在多个可能的异步中断（INT1，INTN）中优先确认一个，这种装置包括优先网络（5），锁存（7）和验证电路（11,12） 。 优先级网络直接在其输入端接收异步中断信号，并在其输出端提供与其输入端子上存在的最高优先级中断相对应的二进制码。 中断代码被锁存在寄存器中并存在于其输出端子上。 锁存在寄存器中的代码由验证电路用作相关输入中断信号的选择代码。 如果存在这样的信号，则验证代码，即将其传送到系统的中央单元。 如果选择的中断信号不存在，则代码不被验证。