公开(公告)号：US20120054402A1

公开(公告)日：2012-03-01

申请号：US12870145

申请日：2010-08-27

申请人： Dhinesh Sasidaran ,  Asad Azam ,  Zeeshan Sarwar

发明人： Dhinesh Sasidaran ,  Asad Azam ,  Zeeshan Sarwar

IPC分类号： G06F13/40

CPC分类号： G06F13/4282 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

摘要： An embodiment may include circuitry to communicatively couple, at least in part, a serial bus controller to at least one serial bus device. The circuitry may have at least one port to be communicatively coupled to the at least one device. The circuitry may route, at least in part, at least one packet issued, at least in part, from the controller to the at least one device via the at least one port based at least in part upon at least one address. The circuitry may associate, at least in part, the at least one address with the at least one port. The at least one address may be assigned, at least in part, to the at least one device by the controller as a result, at least in part, of enumeration, at least in part, of the at least one device by the controller.

摘要翻译： 一个实施例可以包括至少部分地将串行总线控制器通信地耦合到至少一个串行总线设备的电路。 电路可以具有至少一个端口以通信地耦合到至少一个设备。 该电路至少部分地至少部分地至少部分地基于至少一个地址路由至少部分地经由至少一个端口从控制器发送到至少一个设备的至少一个分组。 该电路可以至少部分地将至少一个地址与至少一个端口相关联。 所述至少一个地址可以至少部分地由所述控制器分配给所述至少一个设备，至少部分地由所述控制器至少部分地列举所述至少一个设备。

公开(公告)号：US20110099306A1

公开(公告)日：2011-04-28

申请号：US12980636

申请日：2010-12-29

申请人： Asad Azam ,  Eng Hun Ooi ,  Soon Seng Seh

发明人： Asad Azam ,  Eng Hun Ooi ,  Soon Seng Seh

IPC分类号： G06F13/10

CPC分类号： G06F13/387

摘要： In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于从主机控制器发送帧信息结构（FIS）消息或在主机控制器处接收FIS消息的方法，其将来自主机控制器的同步信号发送到耦合到主机的端口倍增器 控制器，并且从主机控制器向端口倍增器维持发送就绪信号，从而在发送同步信号之后锁定主机控制器和端口倍增器之间的链路，并且从主机控制器向端口发送多个命令FIS消息 乘法器以背对背方式进行，其中背靠背命令FIS消息被定向到不同的设备。 描述和要求保护其他实施例。

公开(公告)号：US20090006657A1

公开(公告)日：2009-01-01

申请号：US11821874

申请日：2007-06-26

申请人： Asad Azam ,  Eng Hun Ooi ,  Soon Seng Seh

发明人： Asad Azam ,  Eng Hun Ooi ,  Soon Seng Seh

IPC分类号： G06F3/00

CPC分类号： G06F13/387

摘要： In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于从主机控制器发送帧信息结构（FIS）消息或在主机控制器处接收FIS消息的方法，其将来自主机控制器的同步信号发送到耦合到主机的端口倍增器 控制器，并且从主机控制器向端口倍增器维持发送就绪信号，从而在发送同步信号之后锁定主机控制器和端口倍增器之间的链路，并且从主机控制器向端口发送多个命令FIS消息 乘法器以背对背方式进行，其中背靠背命令FIS消息被定向到不同的设备。 描述和要求保护其他实施例。

公开(公告)号：US20210326142A1

公开(公告)日：2021-10-21

申请号：US16914331

申请日：2020-06-27

申请人： SUBRATA BANIK ,  ASAD AZAM ,  JENNY M. PELNER ,  VINCENT ZIMMER ,  RAJARAM REGUPATHY

发明人： SUBRATA BANIK ,  ASAD AZAM ,  JENNY M. PELNER ,  VINCENT ZIMMER ,  RAJARAM REGUPATHY

IPC分类号： G06F9/4401 ,  G06F12/0802

摘要： Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

公开(公告)号：US20110302329A1

公开(公告)日：2011-12-08

申请号：US12793535

申请日：2010-06-03

申请人： Asad Azam ,  Dhinesh A/L Sasidaran

发明人： Asad Azam ,  Dhinesh A/L Sasidaran

IPC分类号： G06F12/02 ,  G06F13/20 ,  G06F3/00

CPC分类号： H03K19/1776 ,  G06F13/385 ,  G06F13/4081

摘要： An apparatus comprises a programmable logic device coupled to an interconnect is presented. In one embodiment, the apparatus includes a non-volatile memory to store code for programming the programmable logic device. A controller will program the programmable logic device such that the interconnect is operable in a number of modes associated with a number of input/output devices.

摘要翻译： 提供了一种包括耦合到互连的可编程逻辑器件的装置。 在一个实施例中，该装置包括用于存储用于编程可编程逻辑器件的代码的非易失性存储器。 控制器将对可编程逻辑器件进行编程，使得互连可以与多个输入/输出器件相关联的多个模式中操作。

公开(公告)号：US20190138479A1

公开(公告)日：2019-05-09

申请号：US16236471

申请日：2018-12-29

申请人： Amit Kumar Srivastava ,  Asad Azam

发明人： Amit Kumar Srivastava ,  Asad Azam

IPC分类号： G06F13/40 ,  G06F13/16

摘要： An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.

公开(公告)号：US20120159264A1

公开(公告)日：2012-06-21

申请号：US12970343

申请日：2010-12-16

申请人： Asad Azam ,  Dhinesh Sasidaran

发明人： Asad Azam ,  Dhinesh Sasidaran

IPC分类号： G06F13/10 ,  G06F11/07

CPC分类号： G06F11/07 ,  G06F9/4411 ,  G06F13/10

摘要： Embodiments of the invention are directed towards scalable and dynamically configurable (and reconfigurable) device host controller solutions for system platform controller hubs (PCH). Embodiments of the invention may include logic or modules to detect a device coupled to a common I/O port (alternatively referred to as a converged I/O port) of a host system and determine its device type. Said logic or modules may further load host controller firmware for the device type from a memory to a processing core, such that the processing core will execute the host controller firmware to enable data transfer between the device and the host system. Said processing core may be configured and reconfigured based on the device type connected to the associated common I/O port.

摘要翻译： 本发明的实施例涉及用于系统平台控制器集线器（PCH）的可扩展和可动态配置（和可重新配置的）设备主机控制器解决方案。 本发明的实施例可以包括用于检测耦合到主机系统的公共I / O端口（或称为汇聚I / O端口）的设备并确定其设备类型的逻辑或模块。 所述逻辑或模块可以进一步将用于设备类型的主机控制器固件从存储器加载到处理核心，使得处理核心将执行主机控制器固件以使得能够在设备和主机系统之间进行数据传输。 可以基于连接到相关联的公共I / O端口的设备类型来配置和重新配置所述处理核心。

公开(公告)号：US20200025825A1

公开(公告)日：2020-01-23

申请号：US16586731

申请日：2019-09-27

申请人： Asad Azam ,  Dhinesh A/L Sasidaran ,  R. Selvakumar Raja Gopal

发明人： Asad Azam ,  Dhinesh A/L Sasidaran ,  R. Selvakumar Raja Gopal

IPC分类号： G01R31/3177 ,  G06F11/10 ,  G01R31/317

摘要： Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code.

公开(公告)号：US20200019734A1

公开(公告)日：2020-01-16

申请号：US16584110

申请日：2019-09-26

申请人： R. Selvakumar Raja Gopal ,  Asad Azam

发明人： R. Selvakumar Raja Gopal ,  Asad Azam

IPC分类号： G06F21/76 ,  G01R31/3177 ,  G06F21/60 ,  G06F21/44 ,  H04L9/06 ,  G01R31/317

摘要： Various systems and methods for implementing secure system-on-chip (SoC) debugging are described herein. A method of providing secure system-on-a-chip (SoC) debugging, comprises: receiving, from a remote host at a debug companion circuit, a debug initiation request to initiate a debugging session with an SoC associated with the debug companion circuit; encrypting, at the debug companion circuit, a debug handshake command; transmitting the debug handshake command to the SoC from the debug companion circuit, wherein the SoC is configured to authenticate the debug companion circuit, and configure intellectual property (IP) blocks on the SoC to expose debug data to the debug companion circuit in response to authenticating the debug companion circuit; and managing a secure connection with the SoC to obtain debug data and report the debug data to the remote host.

公开(公告)号：US08812746B2

公开(公告)日：2014-08-19

申请号：US12970343

申请日：2010-12-16

申请人： Asad Azam ,  Dhinesh Sasidaran

发明人： Asad Azam ,  Dhinesh Sasidaran

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F11/07 ,  G06F13/10

CPC分类号： G06F11/07 ,  G06F9/4411 ,  G06F13/10

摘要： Embodiments of the invention are directed towards scalable and dynamically configurable (and reconfigurable) device host controller solutions for system platform controller hubs (PCH). Embodiments of the invention may include logic or modules to detect a device coupled to a common I/O port (alternatively referred to as a converged I/O port) of a host system and determine its device type. Said logic or modules may further load host controller firmware for the device type from a memory to a processing core, such that the processing core will execute the host controller firmware to enable data transfer between the device and the host system. Said processing core may be configured and reconfigured based on the device type connected to the associated common I/O port.

摘要翻译： 本发明的实施例涉及用于系统平台控制器集线器（PCH）的可扩展和可动态配置（和可重新配置的）设备主机控制器解决方案。 本发明的实施例可以包括用于检测耦合到主机系统的公共I / O端口（或称为汇聚I / O端口）的设备并确定其设备类型的逻辑或模块。 所述逻辑或模块可以进一步将用于设备类型的主机控制器固件从存储器加载到处理核心，使得处理核心将执行主机控制器固件以使得能够在设备和主机系统之间进行数据传输。 可以基于连接到相关联的公共I / O端口的设备类型来配置和重新配置所述处理核心。