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公开(公告)号：US20160056762A1
公开(公告)日：2016-02-25
申请号：US14831091
申请日：2015-08-20
Applicant: Augusto Ronchini Ximenes , Robert Bogdan Staszewski
Inventor： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
IPC: H03B5/12
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。
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2.发明授权Split transformer based digitally controlled oscillator and DC-coupled buffer circuit therefor 有权基于分立变压器的数控振荡器和直流耦合缓冲电路公开(公告)号：US09401677B2
公开(公告)日：2016-07-26
申请号：US14831119
申请日：2015-08-20
Applicant: Augusto Ronchini Ximenes , Robert Bogdan Staszewski
Inventor： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
IPC: H03B5/12 , H03B1/00 , H03K3/015 , G04F10/00 , H03L7/08 , H03M1/00 , H03L7/093 , H03M1/20 , H03L7/089 , H03L7/197 , H03K3/03
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。
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3.发明申请Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter 有权分数N全数字锁相环结合前瞻时间到数字转换器公开(公告)号：US20160056825A1
公开(公告)日：2016-02-25
申请号：US14831781
申请日：2015-08-20
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.
Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。
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Patent Agency Ranking
公开(公告)号：US09722537B2
公开(公告)日：2017-08-01
申请号：US14831784
申请日：2015-08-20
IPC: H03B1/00 , H03K3/015 , H03L7/093 , H03B5/12 , G04F10/00 , H03L7/08 , H03M1/00 , H03M1/20 , H03L7/089 , H03L7/197 , H03K3/03
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.
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公开(公告)号：US20160056799A1
公开(公告)日：2016-02-25
申请号：US14831119
申请日：2015-08-20
Applicant: Augusto Ronchini Ximenes , Robert Bogdan Staszewski
Inventor： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。
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6.发明授权Fractional-N all digital phase locked loop incorporating look ahead time to digital converter 有权分数N全数字锁相环结合了数字转换器的前瞻时间公开(公告)号：US09455667B2
公开(公告)日：2016-09-27
申请号：US14831781
申请日：2015-08-20
IPC: H03M1/82 , H03B5/12 , H03B1/00 , H03K3/015 , G04F10/00 , H03L7/08 , H03M1/00 , H03L7/093 , H03M1/20 , H03L7/089 , H03L7/197 , H03K3/03
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.
Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。
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公开(公告)号：US09374036B2
公开(公告)日：2016-06-21
申请号：US14831091
申请日：2015-08-20
Applicant: Augusto Ronchini Ximenes , Robert Bogdan Staszewski
Inventor： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
IPC: H03B5/12 , H03B1/00 , H03K3/015 , G04F10/00 , H03L7/08 , H03M1/00 , H03L7/093 , H03M1/20 , H03L7/089 , H03L7/197 , H03K3/03
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
Abstract translation: 一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。 该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。 该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。
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8.发明申请Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair 有权分数N频率合成器结合循环数字时间和时间到数字电路对公开(公告)号：US20160056827A1
公开(公告)日：2016-02-25
申请号：US14831784
申请日：2015-08-20
CPC classification number: H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
Abstract: A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.
Abstract translation: 数字转换器（TDC）的新颖有用的超前时间，适用于全数字锁相环（ADPLL）作为分数相位误差检测器。 利用频率/锁相期间相位误差的确定性来实现TDC功耗的降低。 先行TDC电路用于构造循环DTC-TDC对，其通过随机旋转循环DTC-TDC结构来减少近整数通道中的输出频谱的分数杂散，使其从每个参考的不同点开始 从而平均化元件的不匹配。 还提出了相关的旋转和抖动方法。 使用前瞻TDC和/或循环DTC-TDC对电路来实现ADPLL。
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