公开(公告)号：US08546203B1

公开(公告)日：2013-10-01

申请号：US13551100

申请日：2012-07-17

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Nicolas Loubet ,  Amlan Majumdar ,  Stefan Schmitz

IPC: H01L21/00

CPC classification number: H01L21/84 ,  H01L29/66628

Abstract: Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract translation: 形成半导体结构的方法包括具有PFET部分和NFET部分的极薄的绝缘上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，与 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在半导体结构上形成低质量的氮化物和高质量的氮化物。 NFET部分中的高质量氮化物被离子注入损坏以便于其去除。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的高质量氮化物被离子注入损坏以便于其去除。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US20110163449A1

公开(公告)日：2011-07-07

申请号：US12683465

申请日：2010-01-07

Applicant: James J. Kelly ,  Veeraghavan S. Basker ,  Bala S. Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

Inventor： James J. Kelly ,  Veeraghavan S. Basker ,  Bala S. Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

Abstract translation: 根据本发明的一个方面，提供了一种用于制造具有接触通孔的半导体元件的方法。 在这种方法中，可以在电介质层中形成孔以至少部分地暴露包括半导体或导电材料中的至少一种的区域。 种子层可以沉积在电介质层的主表面上并且在孔内的表面上。 在一个实施方案中，种子层可以包括选自铱，锇，钯，铂，铑和钌的金属。 基本上由钴组成的层可以电镀在孔内的种子层上，以形成与该区域导电连通的接触通孔。

公开(公告)号：US08691687B2

公开(公告)日：2014-04-08

申请号：US12683465

申请日：2010-01-07

Applicant: James J. Kelly ,  Veeraghavan S. Basker ,  Bala S. Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

Inventor： James J. Kelly ,  Veeraghavan S. Basker ,  Bala S. Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

IPC: H01L21/20 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

公开(公告)号：US20140024181A1

公开(公告)日：2014-01-23

申请号：US13551054

申请日：2012-07-17

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

IPC: H01L21/8238

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract translation: 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，高质量氮化物间隔物 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US08673699B2

公开(公告)日：2014-03-18

申请号：US13551054

申请日：2012-07-17

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

IPC: H01L21/00

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract translation: 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，邻近 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。