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    SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES
    1.
    发明申请
    SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES 有权
    超级金属接触VIAS用于​​半导体器件

    公开(公告)号：US20110163449A1

    公开(公告)日：2011-07-07

    申请号：US12683465

    申请日：2010-01-07

    申请人： James J. Kelly ,  Veeraghavan S. Basker ,  Bala S. Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

    发明人： James J. Kelly ,  Veeraghavan S. Basker ,  Bala S. Haran ,  Soon-Cheon Seo ,  Tuan A. Vo

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

    摘要翻译： 根据本发明的一个方面，提供了一种用于制造具有接触通孔的半导体元件的方法。 在这种方法中，可以在电介质层中形成孔以至少部分地暴露包括半导体或导电材料中的至少一种的区域。 种子层可以沉积在电介质层的主表面上并且在孔内的表面上。 在一个实施方案中，种子层可以包括选自铱，锇，钯，铂，铑和钌的金属。 基本上由钴组成的层可以电镀在孔内的种子层上，以形成与该区域导电连通的接触通孔。

    Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect
    6.
    发明授权
    Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect 有权
    芯片到布线接口，单个金属合金层应用于铜互连表面

    公开(公告)号：US06573606B2

    公开(公告)日：2003-06-03

    申请号：US09881444

    申请日：2001-06-14

    申请人： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

    发明人： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

    IPC分类号： H01L2144

    CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

    摘要翻译： 在本发明中，提供了电隔离的铜互连结构界面，其涉及单个约50-300A厚的合金覆盖层，其控制互连部件的扩散和电迁移并且降低互连的整体有效介电常数; 封盖层被本领域中称为材料所包围的材料包围，其可以为随后的反应离子蚀刻操作提供抗蚀剂，并且还提供了在结构界面的制造中涉及无电沉积的相互依赖的工艺步骤。 本发明中的单层合金金属阻挡层是一般型AXY的合金，其中A是从钴（Co）和镍（Ni）中取出的金属，X是取自钨（W ），锡（Sn）和硅（Si），Y是从磷（P）和硼（B）取代的成员; 厚度在50至300埃的范围内。

    Method to generate porous organic dielectric
    9.
    发明授权
    Method to generate porous organic dielectric 失效
    生成多孔有机电介质的方法

    公开(公告)号：US07101784B2

    公开(公告)日：2006-09-05

    申请号：US11125549

    申请日：2005-05-10

    申请人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

    发明人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

    摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

    摘要翻译： 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。