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1.发明授权
公开(公告)号：US5734275A
公开(公告)日：1998-03-31
申请号：US683685
申请日：1996-07-18
摘要： A programmable logic device (PLD) is presented having an improved sense amplifier. The sense amplifier comprises a cascode-connected pair of transistors coupled between a sense amplifier output and a virtual ground. According to several embodiments, a clipping transistor and a current-channeling transistor can be provided with the sense amplifier to improve its operation. Further, additional current source and current sink transistors can also be added to the sense amplifier design. The clipping transistor helps ensure that any positive-going noise spikes do not deleteriously effect accurate readings of the true value on the input bit line. The current-channeling transistor helps prevent collapse of the bit line caused by significant conductivity of cells connected to the bit line. The combination of clipping and current-channeling provide a relatively narrow voltage range of the bit line voltage, resulting in fast recovery and high speed sensing thereof. The additional current source is used to impute additional current through the amplifying transistor of the cascode-coupled pair of transistors. The additional current sink transistor helps draw the current from the amplifying transistor to a ground supply. Only when the bit line voltage is high will the additional current source and current sink transistors be used.
摘要翻译： 提出了一种具有改进的读出放大器的可编程逻辑器件（PLD）。 感测放大器包括耦合在读出放大器输出和虚拟地之间的共源共栅连接的一对晶体管。 根据几个实施例，限幅晶体管和电流沟道晶体管可以设置有读出放大器以改善其操作。 此外，额外的电流源和电流吸收晶体管也可以添加到读出放大器设计。 削波晶体管有助于确保任何正向噪声尖峰都不会有效地影响输入位线上真实值的精确读数。 电流沟道晶体管有助于防止由连接到位线的单元的显着导电性引起的位线的折叠。 削波和电流沟道的组合提供了比特线电压的相对窄的电压范围，导致快速恢复和高速度感测。 额外的电流源用于通过共源共栅对晶体管对的放大晶体管来补充额外的电流。 额外的电流吸收晶体管有助于将电流从放大晶体管吸取到地电源。 只有当位线电压较高时，才能使用附加电流源和电流吸收晶体管。
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公开(公告)号：US5818294A
公开(公告)日：1998-10-06
申请号：US683373
申请日：1996-07-18
摘要： A circuit is presented which can produce a temperature insensitive, constant current value. The constant current source comprises transistor pairs which mirror a temperature dependent current into a node along with another temperature dependent current. The node thereby receives two temperature dependent currents, wherein one is inversely dependent to that of the other. More specifically, one current increases as temperature increases, whereas the other current decreases as temperature increases. The two currents may thereby be construed to offset one another such that the output of a common node produces a current output which does not change with either an increase or decrease in temperature imputted upon the current source component.
摘要翻译： 提出了可产生温度不敏感，恒定电流值的电路。 恒流源包括将依赖于温度的电流与另一温度相关电流一起反映到节点中的晶体管对。 因此节点接收两个依赖于温度的电流，其中一个与另一个电流成反比。 更具体地，一个电流随温度升高而增加，而另一个电流随温度升高而降低。 因此，两个电流可以被解释为彼此偏移，使得公共节点的输出产生不随着对当前源组件输入的温度的增加或降低而改变的电流输出。
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3.发明授权
公开(公告)号：US5811987A
公开(公告)日：1998-09-22
申请号：US740948
申请日：1996-11-05
申请人： Benjamin Howard Ashmore, Jr. , Jeffery Mark Marshall , Bryon Irwin Moyer , John David Porter , Nicholas A. Schmitz , Bradley A. Sharpe-Geisler
发明人： Benjamin Howard Ashmore, Jr. , Jeffery Mark Marshall , Bryon Irwin Moyer , John David Porter , Nicholas A. Schmitz , Bradley A. Sharpe-Geisler
IPC分类号： H03K3/037 , H03K3/356 , H03K19/173 , H03K19/177 , H03K19/21 , H03K7/38
CPC分类号： H03K3/037 , H03K19/1736 , H03K19/17704 , H03K19/17728 , H03K19/1774 , H03K19/17772 , H03K19/215 , H03K3/0375 , H03K3/356156
摘要： A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.
摘要翻译： 复合非常高密度可编程逻辑器件中的可编程逻辑块的块时钟和初始化电路为可编程逻辑块中的元件生成多个块时钟信号和块初始化信号。 块时钟和初始化电路包括块时钟发生器电路和块初始化电路。 块时钟发生器电路以多个乘积项和多个时钟信号作为输入信号接收第一组乘积项。 响应于输入信号，块时钟发生器电路在多个块时钟线上产生输出信号。 块初始化电路接收多个乘积项中的第二组乘积项作为输入信号。 响应于输入信号，块初始化电路在块初始化线上产生多个输出信号。
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