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6 条记录 (耗时 0.013 秒)

    Sense amplifier based flip-flop
    1.
    发明授权
    Sense amplifier based flip-flop 有权
    基于感应放大器的触发器

    公开(公告)号：US6107853A

    公开(公告)日：2000-08-22

    申请号：US189065

    申请日：1998-11-09

    申请人： Borivoje Nikolic ,  Wenyan Jia

    发明人： Borivoje Nikolic ,  Wenyan Jia

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356191 ,  H03K3/356139

    摘要： A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and Q. These signals have equal rising and falling transitions with the same delays for the Q signal and the Q signal. The second stage has symmetrical pull-up and pull-down circuits.

    摘要翻译： 包括第一阶段和第二阶段的触发器。 第一级接收一对差分信号以产生置位和复位信号。 置位和复位信号的补码产生输出信号Q和+ E，ovs Q + EE。 这些信号具有相同的上升和下降转换，对于Q信号和+ E，ovs Q + EE信号具有相同的延迟。 第二级具有对称的上拉和下拉电路。

    Sliding block (rate 8/9) trellis code for magnetic recording
    2.
    发明授权
    Sliding block (rate 8/9) trellis code for magnetic recording 失效
    滑块（速率8/9）用于磁记录的网格代码

    公开(公告)号：US6081210A

    公开(公告)日：2000-06-27

    申请号：US76717

    申请日：1998-05-13

    申请人： Borivoje Nikolic ,  Ming-Tak Leung

    发明人： Borivoje Nikolic ,  Ming-Tak Leung

    IPC分类号： H03M13/05 ,  H03M7/00

    CPC分类号： H03M13/05

    摘要： A method and system for encoding user data bits for magnetic recording channels that produces a stationary trellis and that limits the burst error propagation to three user bytes. The input data bits are grouped into even bytes and odd bytes. The even bytes are encoded first into even codewords, then each of the odd bytes is encoded into odd codewords based on the even codeword for the even byte preceding each odd byte and on the even codeword for the even byte following each odd byte. The encoding eliminates the most common error events associated with Partial Response Maximum Likelihood channels by: (i) disallowing sequences of four consecutive ones in the codewords, (ii) allowing sequences of three consecutive ones to begin only on certain bit positions in certain codewords, (iii) allowing only certain beginning sequences and ending sequences for odd and even codewords in specific situations, and (iv) changing specific bits in the odd and even codewords based on disallowed codeword sequences.

    摘要翻译： 用于编码用于产生固定网格的磁记录通道的用户数据位的方法和系统，并且将突发错误传播限制到三个用户字节。 输入数据位分为偶数字节和奇数字节。 偶数字节首先被编码为偶数码字，然后基于每个奇数字节之前的偶数字节的偶数码字和每个奇数字节之后的偶数字节的偶数码字，将奇数字节中的每一个编码为奇数码字。 该编码通过以下方式消除了与部分响应最大似然信道相关联的最常见的错误事件：（i）禁止码字中的四个连续序列的序列，（ii）允许三个连续的序列的序列仅在某些码字中的某些比特位置开始， （iii）在特定情况下仅允许奇数和偶数码字的某些起始序列和结束序列，以及（iv）基于不允许的码字序列改变奇数和偶数码字中的特定比特。

    Sense amplifier-based flip-flop with asynchronous set and reset
    3.
    发明授权
    Sense amplifier-based flip-flop with asynchronous set and reset 有权
    基于放大器的触发器，具有异步设置和复位功能

    公开(公告)号：US06633188B1

    公开(公告)日：2003-10-14

    申请号：US09248957

    申请日：1999-02-12

    申请人： Wenyan Jia ,  Borivoje Nikolic

    发明人： Wenyan Jia ,  Borivoje Nikolic

    IPC分类号： H03K312

    CPC分类号： H03K3/356139 ,  G11C7/065 ,  H03K3/35625

    摘要： A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.

    摘要翻译： 包括第一阶段和第二阶段的触发器。 第一级接收一对差分信号以产生置位和复位信号。 置位和复位信号的补码产生输出信号Q和{过滤（Q'），这些信号具有上升和下降晶体管，具有与Q信号相同的延迟和{过滤（Q信号），第二级具有对称上拉 和下拉电路。

    FINFET-BASED SRAM WITH FEEDBACK
    5.
    发明申请
    FINFET-BASED SRAM WITH FEEDBACK 审中-公开
    具有反馈功能的基于FINFET的SRAM

    公开(公告)号：US20070183185A1

    公开(公告)日：2007-08-09

    申请号：US11622305

    申请日：2007-01-11

    申请人： Zheng Guo ,  Sriram Balasubramanian ,  Radu Zlatanovici ,  Tsu-Jae King ,  Borivoje Nikolic

    发明人： Zheng Guo ,  Sriram Balasubramanian ,  Radu Zlatanovici ,  Tsu-Jae King ,  Borivoje Nikolic

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785

    摘要： Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

    摘要翻译： 当前体硅Si MOSFET中的固有变化和具有挑战性的泄漏控制迫使不需要的折衷，并限制了SRAM电路的缩放。 本文教导了改善SRAM单元中的泄漏和噪声容限的电路和机构，例如包括六晶体管（6-T）SRAM单元设计或四晶体管（4-T）SRAM单元设计）的那些。 本发明的SRAM单元利用将存储节点的一部分耦合到存取晶体管的后栅极的反馈装置。 反馈优选以这种方式耦合到两个存取晶体管。 使用这种内置反馈设计的SRAM单元实现了细胞静态噪声容限（SNM）的显着改进，无区域损失。 反馈方案的使用还导致创建了实用的基于4-T FinFET的SRAM单元，其实现了每个100pA的每个电池的待机电流，并且具有与具有反馈的6-T电池相似的SNM改进。