公开(公告)号：US20070183185A1

公开(公告)日：2007-08-09

申请号：US11622305

申请日：2007-01-11

申请人： Zheng Guo ,  Sriram Balasubramanian ,  Radu Zlatanovici ,  Tsu-Jae King ,  Borivoje Nikolic

发明人： Zheng Guo ,  Sriram Balasubramanian ,  Radu Zlatanovici ,  Tsu-Jae King ,  Borivoje Nikolic

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785

摘要： Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

摘要翻译： 当前体硅Si MOSFET中的固有变化和具有挑战性的泄漏控制迫使不需要的折衷，并限制了SRAM电路的缩放。 本文教导了改善SRAM单元中的泄漏和噪声容限的电路和机构，例如包括六晶体管（6-T）SRAM单元设计或四晶体管（4-T）SRAM单元设计）的那些。 本发明的SRAM单元利用将存储节点的一部分耦合到存取晶体管的后栅极的反馈装置。 反馈优选以这种方式耦合到两个存取晶体管。 使用这种内置反馈设计的SRAM单元实现了细胞静态噪声容限（SNM）的显着改进，无区域损失。 反馈方案的使用还导致创建了实用的基于4-T FinFET的SRAM单元，其实现了每个100pA的每个电池的待机电流，并且具有与具有反馈的6-T电池相似的SNM改进。

公开(公告)号：US20090128221A1

公开(公告)日：2009-05-21

申请号：US12261865

申请日：2008-10-30

申请人： Hei Kam ,  Tsu-Jae King

发明人： Hei Kam ,  Tsu-Jae King

IPC分类号： H01L27/092 ,  H03K17/687

CPC分类号： G11C23/00 ,  B82Y10/00 ,  H01H1/0094

摘要： A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth.

摘要翻译： 采用金属 - 绝缘体 - 金属（MIM）技术的门控纳米机电（NEM）开关及相关设备和方法，可以促进低功耗，辐射硬化，高温电子器件和电路的实现。 在一个示例实施例中，栅电极被配置为悬臂梁，其自由端耦合到MIM堆叠。 当施加的栅极电压产生足够的静电力以克服悬臂梁的机械偏置时，堆叠移动跨越源极和漏极区域的桥接接触。 可以在悬臂梁上添加第二组触点以形成互补的开关结构，或者形成单独的悬臂梁。 响应于静力，可以将开关配置为非易失性。 NEM电路在各种电路类型中提供了许多优点，包括但不限于：逻辑，存储器，睡眠电路，通过电路等。

公开(公告)号：US20090121273A1

公开(公告)日：2009-05-14

申请号：US11664018

申请日：2005-09-22

申请人： Tsu-Jae King ,  Gang Liu ,  Min She

发明人： Tsu-Jae King ,  Gang Liu ,  Min She

IPC分类号： H01L29/68 ,  H01L29/788

CPC分类号： H01L21/28194 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/518

摘要： In a non-volatile semiconductor memory device including a source region separated from a drain region by a channel region and with an electrically floating gate electrode spaced from and overlying the channel region, a flexible member is spaced from the floating gate and capable of being flexed towards the floating gate for depositing or removing electrical charge on the floating gate in response to a voltage potential between the flexible member and the channel region. In one embodiment, the flexible member comprises a contact gate electrode. In another embodiment, only a single gate electrode is employed without a separate floating gate.

摘要翻译： 在非易失性半导体存储器件中，包括通过沟道区域与漏极区域分离的源极区域和与沟道区域间隔开并且覆盖沟道区域的电浮置栅电极，柔性构件与浮动栅极间隔开并能够弯曲 朝向浮动栅极，以响应于柔性构件和沟道区域之间的电压电位在浮栅上沉积或去除电荷。 在一个实施例中，柔性构件包括接触栅电极。 在另一个实施例中，仅使用单个栅电极而没有单独的浮栅。

公开(公告)号：US07141858B2

公开(公告)日：2006-11-28

申请号：US10871338

申请日：2004-06-18

申请人： Igor Polishchuk ,  Pushkar Ranade ,  Tsu-Jae King ,  Chenming Hu

发明人： Igor Polishchuk ,  Pushkar Ranade ,  Tsu-Jae King ,  Chenming Hu

IPC分类号： H01L29/49

CPC分类号： H01L21/28079 ,  H01L21/823842 ,  H01L29/4958

摘要： A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

公开(公告)号：US07016224B2

公开(公告)日：2006-03-21

申请号：US10884576

申请日：2004-07-02

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/38

CPC分类号： G11C11/412 ,  G11C2211/5614

摘要： A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

摘要翻译： 公开了一种双端子硅基负差动电阻（NDR）元件，以实现用于所选应用的一种NDR二极管。 两端子器件基于具有修改的沟道掺杂分布的三端NDR功能FET，其中栅极连接到漏极。 该器件可以通过常规CMOS处理与其他NDR和非NDR元件（包括具有NDR功能的FET）进行集成。 还公开了使用这种NDR两端元件和NDR三端的存储单元。

公开(公告)号：US06979580B2

公开(公告)日：2005-12-27

申请号：US10314785

申请日：2002-12-09

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/51 ,  H01L21/66

CPC分类号： H01L21/28185 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.

公开(公告)号：US20050253133A1

公开(公告)日：2005-11-17

申请号：US11045535

申请日：2005-01-28

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L21/265 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/78 ,  H01L21/2652 ,  H01L21/823462 ,  H01L29/42332

摘要： A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.

摘要翻译： 公开了一种使用常规MOS制造操作在硅基衬底上形成的负差动电阻（NDR）场效应晶体管元件。 还公开了用于改善NDR元件的各种NDR特性的方法，例如峰 - 谷比（PVR），NDR起始电压（V NDR N）和相关参数。

公开(公告)号：US06933548B1

公开(公告)日：2005-08-23

申请号：US10827886

申请日：2004-04-19

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： H01L29/78 ,  H01L29/788 ,  H01L29/80

CPC分类号： H01L29/788 ,  H01L29/78

摘要： A negative differential resistance device is disclosed which is particularly suited as a replacement in memory cells for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The NDR device includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. The NDR device can be shut off during static operations to further reduce power dissipation.

摘要翻译： 公开了一种负差动电阻器件，其特别适用于用于常规上拉和负载元件（例如NDR二极管，无源电阻器和常规FET）的存储器单元中的替换。 NDR器件包括形成在或非常接近衬底（其可以是硅或SOI）和栅绝缘层之间的界面处的电荷俘获层。 NDR设备可以在静态操作期间关闭，以进一步降低功耗。

公开(公告)号：US06855994B1

公开(公告)日：2005-02-15

申请号：US09857453

申请日：1999-11-29

申请人： Ya-Chin King ,  Tsu-Jae King ,  Chen Ming Hu

发明人： Ya-Chin King ,  Tsu-Jae King ,  Chen Ming Hu

IPC分类号： H01L29/78 ,  C23C14/48 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L21/31 ,  H01L21/469 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： C23C14/48 ,  H01L21/823462 ,  Y10S438/92 ,  Y10S438/966 ,  Y10S438/974

摘要： A semiconductor device including a gate oxide of multiple thicknesses for multiple transistors where the gate oxide thicknesses are altered through the growth process of implanted oxygen ions into selected regions of a substrate. The implanted oxygen ions accelerate the growth of the oxide which also allow superior quality and reliability of the oxide layer, where the quality is especially important, compared to inter-metal dielectric layers. A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during oxidation growth process by implanting nitrogen into selected regions of the substrate, which the nitrogen ions retard the growth of the silicon oxide resulting in a diminished oxide quality. Therefore it is desirable to fabricate a semiconductor device with multiple thicknesses of gate oxide by the implanted oxygen ion technique.

摘要翻译： 一种半导体器件，包括多个晶体管的多个厚度的栅极氧化物，其中栅极氧化物厚度通过将氧离子注入到衬底的选定区域的生长过程而改变。 植入的氧离子加速了氧化物的生长，这也使得与金属间介电层相比，质量特别重要的氧化物层的质量和可靠性也是优异的。 已经使用了一种技术来改变在氧化生长过程中在硅晶片上生长的氧化物层的厚度，这是通过将氮气注入衬底的选定区域来实现的，氮离子阻碍氧化硅的生长，导致氧化物质量降低。 因此，期望通过注入的氧离子技术制造具有多个栅极氧化物厚度的半导体器件。

公开(公告)号：US06853035B1

公开(公告)日：2005-02-08

申请号：US10831867

申请日：2004-04-26

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C5/00 ,  G11C11/412 ,  H01L29/76

CPC分类号： G11C11/4125 ,  G11C5/005

摘要： An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAW using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

摘要翻译： 公开了一种有源负差分电阻元件（NDR FET）和存储器件（例如使用这种元件的SRAW），通过调节电荷陷阱的位置来增强NDR FET和这种存储器件的软错误率（SER）性能 负责捕获层，负责实现NDR行为，SER和开关速度性能特性可以通过适当放置充电陷阱来定制。