公开(公告)号：US09734116B2

公开(公告)日：2017-08-15

申请号：US14658021

申请日：2015-03-13

申请人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

发明人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

IPC分类号： G06F13/14 ,  G06F13/42 ,  G06F13/12

CPC分类号： G06F13/4221 ,  G06F13/122 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

公开(公告)号：US20150269108A1

公开(公告)日：2015-09-24

申请号：US14658021

申请日：2015-03-13

申请人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

发明人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

IPC分类号： G06F13/42

CPC分类号： G06F13/4221 ,  G06F13/122 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

摘要翻译： 用于配置集成电路（IC）芯片以实现协议栈的技术和机制。 在一个实施例中，IC芯片的事务层可操作以与具有与外围组件互连Express（TM TM）规范中定义的格式兼容的格式的IC芯片事务层分组（TLP）的链路层进行交换。 IC芯片的配置电路提供包括交易层，链路层的电路和IC芯片的第一物理层的第一协议栈的配置。 配置电路还提供包括交易层，链路层的电路和IC芯片的第二物理层的第二协议栈的备选配置。 在另一实施例中，第一协议栈支持单端信令来传送TLP信息，而第二协议栈支持差分信令来传送TLP信息。

公开(公告)号：US20180060085A1

公开(公告)日：2018-03-01

申请号：US15252529

申请日：2016-08-31

申请人： Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Anupama Suryanarayanan ,  Ameya Ambardekar ,  Craig Topper ,  Eric R. Heit ,  Joseph M. Alberts

发明人： Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Anupama Suryanarayanan ,  Ameya Ambardekar ,  Craig Topper ,  Eric R. Heit ,  Joseph M. Alberts

IPC分类号： G06F9/44 ,  G06F12/0897 ,  G06F12/0875 ,  G06F12/084 ,  G06F12/0842 ,  G06F1/28

摘要： In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.

公开(公告)号：US09753516B2

公开(公告)日：2017-09-05

申请号：US13335628

申请日：2011-12-22

申请人： Ryan D. Wells ,  Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Gary A. Andrew

发明人： Ryan D. Wells ,  Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Gary A. Andrew

IPC分类号： G06F1/00 ,  G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/324 ,  Y02D10/126

摘要： According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.

公开(公告)号：US08539269B2

公开(公告)日：2013-09-17

申请号：US13077618

申请日：2011-03-31

申请人： Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Doron Rajwan ,  Kosta Luria ,  Ronny Korner ,  Dan Baum

发明人： Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Doron Rajwan ,  Kosta Luria ,  Ronny Korner ,  Dan Baum

IPC分类号： G06F1/32

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3243 ,  G06F11/004 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/86 ,  Y02D10/152

摘要： An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.

摘要翻译： 设备可以包括处理器的一个或多个处理器核心和一组限流器。 每个限流器可以耦合到相应的处理器核心并且被布置成监视处理器中的处理器活动，以将处理器活动与多个电流限制的一个或多个电流限制进行比较; 并且当超过一个或多个电流限制时启动限流动作。

公开(公告)号：US20130179705A1

公开(公告)日：2013-07-11

申请号：US13782539

申请日：2013-03-01

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessmann ,  Ryan Wells ,  Nadav Shulman

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Wiessmann ,  Ryan Wells ,  Nadav Shulman

IPC分类号： G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

公开(公告)号：US20120221873A1

公开(公告)日：2012-08-30

申请号：US13335628

申请日：2011-12-22

申请人： Ryan D. Wells ,  Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Gary A. Andrew

发明人： Ryan D. Wells ,  Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Gary A. Andrew

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/324 ,  Y02D10/126

摘要： According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.

摘要翻译： 根据本发明的一个实施例，集成电路设备包括一个或多个处理器核和耦合到处理器核的控制单元。 控制单元适于基于代替功率电平的估计的活动水平来控制至少一个处理器核心的工作频率。 估计的活动水平与估计的功率水平不同，独立于该集成电路设备特有的泄漏功率和电压特性。

公开(公告)号：US20210064426A1

公开(公告)日：2021-03-04

申请号：US16554940

申请日：2019-08-29

申请人： Praveen Kumar Gupta ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Stephen H. Gunther

发明人： Praveen Kumar Gupta ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Stephen H. Gunther

IPC分类号： G06F9/48 ,  G06F1/3206 ,  G06F9/50 ,  G06F1/08 ,  G06F1/10

摘要： In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

公开(公告)号：US09606595B2

公开(公告)日：2017-03-28

申请号：US13994065

申请日：2011-12-30

申请人： Ankush Varma ,  Jeremy J. Shrall ,  Krishnakanth Venkata Sistla ,  Avinash N. Ananthakrishnan ,  Vivek Garg ,  Christopher A. Poirier, Sr. ,  Martin T. Rowland ,  Edward R. Stanford

发明人： Ankush Varma ,  Jeremy J. Shrall ,  Krishnakanth Venkata Sistla ,  Avinash N. Ananthakrishnan ,  Vivek Garg ,  Christopher A. Poirier, Sr. ,  Martin T. Rowland ,  Edward R. Stanford

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F11/30

CPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3293 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3058

摘要： Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.

公开(公告)号：US09141166B2

公开(公告)日：2015-09-22

申请号：US13324932

申请日：2011-12-13

申请人： Krishnakanth V. Sistla ,  Martin T. Rowland ,  Cesar A. Quiroz ,  Joseph R. Doucette ,  Gopikrishna Jandhyala ,  Kai Cheng ,  Celeste M. Brown ,  Avinash N. Ananthakrishnan

发明人： Krishnakanth V. Sistla ,  Martin T. Rowland ,  Cesar A. Quiroz ,  Joseph R. Doucette ,  Gopikrishna Jandhyala ,  Kai Cheng ,  Celeste M. Brown ,  Avinash N. Ananthakrishnan

IPC分类号： G06F13/14 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3206

摘要： An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.

摘要翻译： 这里描述了用于动力域的动态功率控制的装置，方法和系统。 提供了一个时间窗口的功率限制。 在控制环路周期内，电源接口决定了电力领域的能源消耗，智能地根据能源消耗在电力领域的设备之间预算功率，将这些预算转换为电力域的性能最大值，并限制了电力领域的设备性能。 功率域使用运行平均功率限制来达到性能最大值。