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    Apparatus and method using different size rename registers for partial-bit and bulk-bit writes
    2.
    发明授权
    Apparatus and method using different size rename registers for partial-bit and bulk-bit writes 有权
    使用不同大小的重命名寄存器进行部分位和批量位写入的装置和方法

    公开(公告)号：US07428631B2

    公开(公告)日：2008-09-23

    申请号：US10632432

    申请日：2003-07-31

    申请人： Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Bryan P. Black

    发明人： Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Bryan P. Black

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3836 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30112 ,  G06F9/384

    摘要： An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.

    摘要翻译： 提供了一种装置和方法，用于重命名允许不同长度的比特访问的逻辑寄存器，例如谓词寄存器。 重命名逻辑支持对部分位访问和对寄存器的位的批量访问进行重命名。 重命名逻辑利用与逻辑寄存器相关联的重命名映射表来重命名，并且还包括多个物理重命名寄存器。 它们的物理重命名寄存器包括一组用于部分位写入重命名的瘦物理重命名寄存器。 物理重命名寄存器还包括一组用于批量位写入重命名的胖物理重命名寄存器。 还可以使用附加大小的物理重命名寄存器。 单个物理重命名映射表的条目可能指向胖或瘦身体重命名寄存器。

    Data processor with branch target address cache and method of operation
    4.
    发明授权
    Data processor with branch target address cache and method of operation 失效
    数据处理器具有分支目标地址缓存和操作方法

    公开(公告)号：US5805877A

    公开(公告)日：1998-09-08

    申请号：US718027

    申请日：1996-09-23

    申请人： Bryan P. Black ,  Marvin A. Denman, Jr. ,  Seungyoon Peter Song

    发明人： Bryan P. Black ,  Marvin A. Denman, Jr. ,  Seungyoon Peter Song

    IPC分类号： G06F9/38 ,  G06F9/32

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.

    摘要翻译： 数据处理器（10）具有存储多个最近遇到的提取地址目标地址对的BTAC（48）。 分支单元（20）生成取决于先决条件和接收到的分支指令的取出地址。 在执行每个分支指令之后，分支单元预测下一次遇到相同的分支指令时是否满足条件先例。 如果先决条件的预测值将导致分支，则分支单元将对应于分支指令的获取地址 - 目标地址对添加到BTAC。 如果先决条件的预测值不会导致分支，则分支单元从BTAC删除与分支指令相对应的获取地址 - 目标地址对。

    Data processor with branch target address cache and method of operation
    5.
    发明授权
    Data processor with branch target address cache and method of operation 失效
    数据处理器具有分支目标地址缓存和操作方法

    公开(公告)号：US5530825A

    公开(公告)日：1996-06-25

    申请号：US228469

    申请日：1994-04-15

    申请人： Bryan P. Black ,  Marvin A. Denman

    发明人： Bryan P. Black ,  Marvin A. Denman

    IPC分类号： G06F9/38 ,  G06F9/32

    CPC分类号： G06F9/3806

    摘要： A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution address that depends upon one of the plurality of instructions. After executing each instruction, the branch unit may delete an entry from the BTAC if the instruction's execution address differs from the target address and if the instruction is the same instruction which generated the BTAC entry initially.

    摘要翻译： 数据处理器（10）具有存储多个最近遇到的提取地址目标地址对的BTAC（48）。 每一对还包括一个偏移标签，用于标识由获取地址生成的条目索引的多个指令中的哪一个。 分支单元（20）产生取决于多个指令之一的执行地址。 在执行每条指令之后，如果指令的执行地址与目标地址不同，并且指令是最初生成BTAC条目的指令相同的指令，则分支单元可以从BTAC中删除一个条目。

    Efficient instruction scheduling with lossy tracking of scheduling information
    7.
    发明授权
    Efficient instruction scheduling with lossy tracking of scheduling information 失效
    有效的指令调度与有序的跟踪调度信息

    公开(公告)号：US07130990B2

    公开(公告)日：2006-10-31

    申请号：US10334528

    申请日：2002-12-31

    申请人： Edward A. Brekelbaum ,  Bryan P. Black ,  Jeffrey P. Rupley, II

    发明人： Edward A. Brekelbaum ,  Bryan P. Black ,  Jeffrey P. Rupley, II

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

    摘要： A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.

    摘要翻译： 提供了一种用于向调度器提供就绪信息的方法和装置。 依赖信息保存在相对较小的地图表中，当依赖信息超过地图表中的可用空间时，可能会丢失信息。 在选择队列中，随着空间允许，维护就绪指令。 调度指令的标签保存在查找队列中，并且随着空间允许，调度指令的依赖关系信息保持在更新队列中。 基于更新队列中的信息更新调度窗口中的指令的就绪信息。 由于空间限制，映射表，查找队列，更新队列和/或选择队列可能会导致指令信息丢失。 丢失指令的调度由有损指令处理程序处理。

    Data processor with branch prediction and method of operation
    8.
    发明授权
    Data processor with branch prediction and method of operation 失效
    具有分支预测和操作方法的数据处理器

    公开(公告)号：US5761723A

    公开(公告)日：1998-06-02

    申请号：US637189

    申请日：1996-04-08

    申请人： Bryan P. Black ,  Marvin Denman ,  Mark A. Kearney ,  Seungyoon Peter Song

    发明人： Bryan P. Black ,  Marvin Denman ,  Mark A. Kearney ,  Seungyoon Peter Song

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3806 ,  G06F9/3844 ,  G06F9/3861

    摘要： A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.

    摘要翻译： 数据处理器（10）具有分支目标地址高速缓冲存储器（48），用于存储多个最近采取的分支指令的目标地址。 通常，将每个获取地址与分支目标地址高速缓存的内容进行比较。 如果发生命中，则数据处理器分支到缓存的目标地址。 数据处理器还具有一个调度单元（60），当分支目标地址缓存器确定分支目标地址高速缓冲存储器“完全不是分支指令”的指令时，使分配目标地址缓存中存储的数据无效， 幻影分支“。 因此，数据处理器在上下文切换之后自动使其分支目标地址高速缓存数据失效。

    Method of operating a data processor with rapid address comparison for data forwarding
    9.
    发明授权
    Method of operating a data processor with rapid address comparison for data forwarding 失效
    用于数据转发的快速地址比较操作数据处理器的方法

    公开(公告)号：US5613081A

    公开(公告)日：1997-03-18

    申请号：US526398

    申请日：1995-09-11

    申请人： Bryan P. Black ,  Marvin A. Denman

    发明人： Bryan P. Black ,  Marvin A. Denman

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

    CPC分类号： G06F9/3802 ,  G06F12/0859

    摘要： A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.

    摘要翻译： 数据处理器（10）具有用于产生每个请求数据双字的地址的执行单元（18,20）。 数据处理器在数据处理器的存储器高速缓存中未找到所请求的双字时，提取整个存储器行，四个双字数据，其中包含所请求的双字。 当从外部存储器系统返回时，数据处理器最终将所请求的数据存储在存储器高速缓存（40）中。 数据处理器还具有用于在某些情况下将先前请求的双字直接转发到执行单元的转发电路（48,50）。 如果数据处理器自上次存储器高速缓存未命中以来没有超过存储器线边界，并且所请求和接收的双字的两个最低有效位逻辑上匹配，转发电路将转发所请求的双字。