公开(公告)号：US20180012869A1

公开(公告)日：2018-01-11

申请号：US15695291

申请日：2017-09-05

申请人： Sony Semiconductor Solutions Corporation

发明人： Mariam Sadaka

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/367 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09051 ,  H01L2224/09519 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00012 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/03 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014

摘要： Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods.

公开(公告)号：US09859235B2

公开(公告)日：2018-01-02

申请号：US12619503

申请日：2009-11-16

申请人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

发明人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/2064 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

公开(公告)号：US09844837B2

公开(公告)日：2017-12-19

申请号：US14006538

申请日：2012-03-23

申请人： Masato Shimamura ,  Tsukasa Ohnishi ,  Mitsuhiro Kosai ,  Kazuyori Takagi ,  Tomoko Nonaka ,  Masayuki Suzuki ,  Toru Hayashida ,  Seiko Ishibashi ,  Shunsaku Yoshikawa ,  Yoshie Yamanaka

发明人： Masato Shimamura ,  Tsukasa Ohnishi ,  Mitsuhiro Kosai ,  Kazuyori Takagi ,  Tomoko Nonaka ,  Masayuki Suzuki ,  Toru Hayashida ,  Seiko Ishibashi ,  Shunsaku Yoshikawa ,  Yoshie Yamanaka

IPC分类号： B23K35/26 ,  B23K35/02 ,  B23K35/36 ,  C22F1/16 ,  C22C13/00 ,  C22C13/02

CPC分类号： B23K35/262 ,  B23K35/0227 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/26 ,  B23K35/3618 ,  C22C13/00 ,  C22C13/02 ,  C22F1/16 ,  H01L2924/00013 ,  H01L2924/014 ,  Y10T428/12222 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： By using a solder alloy consisting essentially of 0.2-1.2 mass % of Ag, 0.6-0.9 mass % of Cu, 1.2-3.0 mass % of Bi, 0.02-1.0 mass % of Sb, 0.01-2.0 mass % of In, and a remainder of Sn, it is possible to obtain portable devices having excellent resistance to drop impact and excellent heat cycle properties without developing thermal fatigue even when used in a high-temperature environment such as inside a vehicle heated by the sun or in a low-temperature environment such as outdoors in snowy weather.

公开(公告)号：US20170339785A1

公开(公告)日：2017-11-23

申请号：US15673696

申请日：2017-08-10

申请人： HARRIS CORPORATION

发明人： LOUIS JOSEPH RENDEK, JR. ,  TRAVIS L. KERBY ,  CASEY PHILIP RODRIGUEZ

IPC分类号： H05K1/03 ,  H05K1/18 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  H05K1/11 ,  H01L21/48 ,  H01L23/00

CPC分类号： H05K1/03 ,  H01L21/4867 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/13599 ,  H01L2224/16111 ,  H01L2224/16238 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0313 ,  H05K1/032 ,  H05K1/111 ,  H05K1/181 ,  H05K3/281 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0141 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

公开(公告)号：US20170148721A1

公开(公告)日：2017-05-25

申请号：US15428007

申请日：2017-02-08

申请人： STATS ChipPAC Pte. Ltd.

发明人： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

公开(公告)号：US20170133338A1

公开(公告)日：2017-05-11

申请号：US15405431

申请日：2017-01-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

公开(公告)号：US09431275B2

公开(公告)日：2016-08-30

申请号：US13209898

申请日：2011-08-15

申请人： Randy Bindrup ,  W. Eric Boyd ,  John Leon ,  James Yamaguchi ,  Angel Pepe

发明人： Randy Bindrup ,  W. Eric Boyd ,  John Leon ,  James Yamaguchi ,  Angel Pepe

IPC分类号： H01L23/488 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L24/45 ,  H01L21/568 ,  H01L23/498 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/45541 ,  H01L2224/82001 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2224/82 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/48

摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

摘要翻译： 一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径， 封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

公开(公告)号：US20160233160A1

公开(公告)日：2016-08-11

申请号：US15133121

申请日：2016-04-19

申请人： Micron Technology, Inc.

发明人： Kyle K. Kirby ,  Kunal R. Parekh ,  Philip J. Ireland ,  Sarah A. Niroumand

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/02063 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.

摘要翻译： 具有通硅通孔的微电子器件及其相关制造方法。 一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。 该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

公开(公告)号：US09412684B2

公开(公告)日：2016-08-09

申请号：US14056047

申请日：2013-10-17

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Anup Bhalla ,  Jun Lu ,  Kai Liu

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

摘要翻译： 半导体封装及其制造方法包括具有管芯焊盘的引线框架和设置在顶表面上的大致V形槽的源极引线。 设置在芯片焊盘上的半导体芯片。 连接到芯片的顶表面电极的金属板具有在V沟槽中终止的弯曲延伸部，与V沟槽侧壁中的至少一个接触。

公开(公告)号：US09406634B2

公开(公告)日：2016-08-02

申请号：US14711864

申请日：2015-05-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： A package includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis, wherein the first work piece is rigid, and an entirety of the metal trace is on the first work piece. The package further includes a second work piece with a plurality of elongated bumps, wherein at least one of the plurality of elongated metal bumps has a second axis and at least another of the plurality of elongated metal bumps has a third axis, wherein the second and the third axes are not the same and the second axis is at a non-zero angle from the first axis, wherein the plurality of elongated bumps are electrically connected to the metal trace.

摘要翻译： 包装包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线，其中第一工件是刚性的，并且整个金属迹线在第一工件上 。 所述封装还包括具有多个细长凸块的第二工件，其中所述多个细长金属凸块中的至少一个具有第二轴线，并且所述多个细长金属凸块中的至少另一个具有第三轴线，其中所述第二和 所述第三轴线不相同，所述第二轴线与所述第一轴线成非零角度，其中所述多个细长凸块电连接到所述金属轨迹。