公开(公告)号：US5613081A

公开(公告)日：1997-03-18

申请号：US526398

申请日：1995-09-11

申请人： Bryan P. Black ,  Marvin A. Denman

发明人： Bryan P. Black ,  Marvin A. Denman

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3802 ,  G06F12/0859

摘要： A data processor (10) has an execution unit (18, 20) for generating the address of each requested data double-word. The data processor fetches the entire memory line, four double-words of data, containing the requested double-word when the requested double-word is not found in the data processor's memory cache. The data processor ultimately stores the requested data in the memory cache (40) when returned from an external memory system. The data processor also has forwarding circuitry (48, 50) for forwarding previously requested double-words directly to the execution unit under certain circumstances. The forwarding circuitry will forward a requested double-word if the data processor has not crossed a memory line boundary since the last memory cache miss and if the two least significant bits of the requested and received double-words logically match.

摘要翻译： 数据处理器（10）具有用于产生每个请求数据双字的地址的执行单元（18,20）。 数据处理器在数据处理器的存储器高速缓存中未找到所请求的双字时，提取整个存储器行，四个双字数据，其中包含所请求的双字。 当从外部存储器系统返回时，数据处理器最终将所请求的数据存储在存储器高速缓存（40）中。 数据处理器还具有用于在某些情况下将先前请求的双字直接转发到执行单元的转发电路（48,50）。 如果数据处理器自上次存储器高速缓存未命中以来没有超过存储器线边界，并且所请求和接收的双字的两个最低有效位逻辑上匹配，转发电路将转发所请求的双字。

公开(公告)号：US5805877A

公开(公告)日：1998-09-08

申请号：US718027

申请日：1996-09-23

申请人： Bryan P. Black ,  Marvin A. Denman, Jr. ,  Seungyoon Peter Song

发明人： Bryan P. Black ,  Marvin A. Denman, Jr. ,  Seungyoon Peter Song

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/3844

摘要： A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.

摘要翻译： 数据处理器（10）具有存储多个最近遇到的提取地址目标地址对的BTAC（48）。 分支单元（20）生成取决于先决条件和接收到的分支指令的取出地址。 在执行每个分支指令之后，分支单元预测下一次遇到相同的分支指令时是否满足条件先例。 如果先决条件的预测值将导致分支，则分支单元将对应于分支指令的获取地址 - 目标地址对添加到BTAC。 如果先决条件的预测值不会导致分支，则分支单元从BTAC删除与分支指令相对应的获取地址 - 目标地址对。

公开(公告)号：US5530825A

公开(公告)日：1996-06-25

申请号：US228469

申请日：1994-04-15

申请人： Bryan P. Black ,  Marvin A. Denman

发明人： Bryan P. Black ,  Marvin A. Denman

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3806

摘要： A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. Each pair also includes an offset tag identifying which one of a plurality of instructions indexed by the fetch address generated the entry. A branch unit (20) generates an execution address that depends upon one of the plurality of instructions. After executing each instruction, the branch unit may delete an entry from the BTAC if the instruction's execution address differs from the target address and if the instruction is the same instruction which generated the BTAC entry initially.

摘要翻译： 数据处理器（10）具有存储多个最近遇到的提取地址目标地址对的BTAC（48）。 每一对还包括一个偏移标签，用于标识由获取地址生成的条目索引的多个指令中的哪一个。 分支单元（20）产生取决于多个指令之一的执行地址。 在执行每条指令之后，如果指令的执行地址与目标地址不同，并且指令是最初生成BTAC条目的指令相同的指令，则分支单元可以从BTAC中删除一个条目。

公开(公告)号：US07171545B2

公开(公告)日：2007-01-30

申请号：US10747625

申请日：2003-12-30

申请人： John P. Devale ,  Bryan P. Black ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II

发明人： John P. Devale ,  Bryan P. Black ,  Edward A. Brekelbaum ,  Jeffrey P. Rupley, II

IPC分类号： G06F9/30

CPC分类号： G06F9/30138

摘要： A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.

摘要翻译： 支持预测寄存器高速缓存分配和输入的机制使用计数器查找表来确定物理寄存器引用的潜在重要性。

公开(公告)号：US09977674B2

公开(公告)日：2018-05-22

申请号：US10685654

申请日：2003-10-14

申请人： Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Edward T. Grochowski ,  Bryan P. Black

发明人： Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Edward T. Grochowski ,  Bryan P. Black

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384

摘要： Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

公开(公告)号：US08110899B2

公开(公告)日：2012-02-07

申请号：US11613774

申请日：2006-12-20

申请人： Paul A. Reed ,  Bryan P. Black

发明人： Paul A. Reed ,  Bryan P. Black

IPC分类号： H01L23/48

CPC分类号： H01L25/0652 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06156 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00

摘要： An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.

摘要翻译： 一种包括包括多个导电通过基板通孔（TSV））的第一管芯的装置; 以及多个第二骰子，每个第二骰子都包括耦合到第一骰子的TSV的多个接触点，所述多个第二骰子被布置成集体地包括接近第一骰子的表面积的表面积。 一种方法，包括在第一管芯上布置多个第二管芯，使得多个第二管芯集体包括接近第一管芯表面积的表面积; 以及将多个第二装置电耦合到多个第一管芯。 一种包括包括印刷电路板和模块的电子设备的系统，所述模块包括包括多个TSV的第一裸片; 并且所述多个第二管芯被布置成共同地包括接近所述第一管芯的表面积的表面积。

公开(公告)号：US20080150088A1

公开(公告)日：2008-06-26

申请号：US11613774

申请日：2006-12-20

申请人： Paul A. Reed ,  Bryan P. Black

发明人： Paul A. Reed ,  Bryan P. Black

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/0652 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06156 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00

摘要： An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.

摘要翻译： 一种包括包括多个导电通过基板通孔（TSV））的第一管芯的装置; 以及多个第二骰子，每个第二骰子都包括耦合到第一骰子的TSV的多个接触点，所述多个第二骰子被布置成集体地包括接近第一骰子的表面积的表面积。 一种方法，包括在第一管芯上布置多个第二管芯，使得多个第二管芯集体包括接近第一管芯表面积的表面积; 以及将多个第二装置电耦合到多个第一管芯。 一种包括包括印刷电路板和模块的电子设备的系统，所述模块包括包括多个TSV的第一裸片; 并且所述多个第二管芯被布置成共同地包括接近所述第一管芯的表面积的表面积。

公开(公告)号：US20090138688A1

公开(公告)日：2009-05-28

申请号：US12365171

申请日：2009-02-04

申请人： Bryan P. Black ,  Nicholas G. Samra ,  M. Clair Webb

发明人： Bryan P. Black ,  Nicholas G. Samra ,  M. Clair Webb

IPC分类号： G06F9/38

CPC分类号： G06F15/7832 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/14 ,  Y02D10/12 ,  Y02D10/13 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

摘要： Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

摘要翻译： 公开了一种多芯片处理器装置和系统。 执行一个或多个指令的处理器逻辑在两个或多个面对面堆叠的骰子之间分配。 处理器包括在堆叠的骰子之间的导电接口，以便于管芯到管芯的通信。

公开(公告)号：US07130990B2

公开(公告)日：2006-10-31

申请号：US10334528

申请日：2002-12-31

申请人： Edward A. Brekelbaum ,  Bryan P. Black ,  Jeffrey P. Rupley, II

发明人： Edward A. Brekelbaum ,  Bryan P. Black ,  Jeffrey P. Rupley, II

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855

摘要： A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.

摘要翻译： 提供了一种用于向调度器提供就绪信息的方法和装置。 依赖信息保存在相对较小的地图表中，当依赖信息超过地图表中的可用空间时，可能会丢失信息。 在选择队列中，随着空间允许，维护就绪指令。 调度指令的标签保存在查找队列中，并且随着空间允许，调度指令的依赖关系信息保持在更新队列中。 基于更新队列中的信息更新调度窗口中的指令的就绪信息。 由于空间限制，映射表，查找队列，更新队列和/或选择队列可能会导致指令信息丢失。 丢失指令的调度由有损指令处理程序处理。

公开(公告)号：US5761723A

公开(公告)日：1998-06-02

申请号：US637189

申请日：1996-04-08

申请人： Bryan P. Black ,  Marvin Denman ,  Mark A. Kearney ,  Seungyoon Peter Song

发明人： Bryan P. Black ,  Marvin Denman ,  Mark A. Kearney ,  Seungyoon Peter Song

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3806 ,  G06F9/3844 ,  G06F9/3861

摘要： A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.

摘要翻译： 数据处理器（10）具有分支目标地址高速缓冲存储器（48），用于存储多个最近采取的分支指令的目标地址。 通常，将每个获取地址与分支目标地址高速缓存的内容进行比较。 如果发生命中，则数据处理器分支到缓存的目标地址。 数据处理器还具有一个调度单元（60），当分支目标地址缓存器确定分支目标地址高速缓冲存储器“完全不是分支指令”的指令时，使分配目标地址缓存中存储的数据无效， 幻影分支“。 因此，数据处理器在上下文切换之后自动使其分支目标地址高速缓存数据失效。