公开(公告)号：US20190303334A1

公开(公告)日：2019-10-03

申请号：US16447025

申请日：2019-06-20

申请人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

发明人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06T1/20

摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

公开(公告)号：US20120185615A1

公开(公告)日：2012-07-19

申请号：US13428079

申请日：2012-03-23

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00 ,  G06F13/42 ,  G06F13/20

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

公开(公告)号：US20100082866A1

公开(公告)日：2010-04-01

申请号：US12286324

申请日：2008-09-30

申请人： Bryan R. White ,  Douglas Moran

发明人： Bryan R. White ,  Douglas Moran

IPC分类号： G06F13/24

CPC分类号： G06F1/3203

摘要： In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.

公开(公告)号：US07269756B2

公开(公告)日：2007-09-11

申请号：US10808000

申请日：2004-03-24

申请人： Sean T. Baartmans ,  Bryan R. White

发明人： Sean T. Baartmans ,  Bryan R. White

IPC分类号： G06F11/00

CPC分类号： G01R31/31705

摘要： In one embodiment, the invention may include a logic structure integrated in an integrated circuit (IC), that has a set of bus inputs to generate events, a mask register to select inputs from among the set of bus inputs, a logic register to select logic to apply to the selected inputs and an event output to supply the result of the applied logic. The embodiment may further include a bus interface integrated in the IC and coupled to the logic structure to transmit settable parameters to the mask register and the logic register of the logic structure from an external agent.

摘要翻译： 在一个实施例中，本发明可以包括集成在集成电路（IC）中的逻辑结构，其具有一组总线输入以产生事件;掩模寄存器，用于从所述总线输入集合中选择输入;逻辑寄存器，用于选择 应用于所选输入的逻辑和事件输出以提供所应用逻辑的结果。 该实施例还可以包括集成在IC中并耦合到逻辑结构的总线接口，以将可设置参数从外部代理发送到掩模寄存器和逻辑结构的逻辑寄存器。

公开(公告)号：US06230228B1

公开(公告)日：2001-05-08

申请号：US09283929

申请日：1999-04-01

申请人： Nick G. Eskandari ,  Bryan R. White

发明人： Nick G. Eskandari ,  Bryan R. White

IPC分类号： G06F1300

CPC分类号： G06F13/4059

摘要： An embodiment of the invention is a bridge having a transaction queue for storing transaction information for each of a number of enqueued posted write transactions, a data queue for simultaneously storing transaction data for each of the enqueued transactions, the transaction data having been received through slave logic of the bridge to be delivered through master logic of the bridge, and a controller for managing the transaction and data queues in response to the transaction information, the bridge being further configured to dynamically allow the transaction data for a single enqueued transaction to occupy the maximum available space in the data queue.

摘要翻译： 本发明的一个实施例是具有用于存储多个入队过的写事务中的每一个的事务信息的事务队列的桥，用于同时存储每个入队事务的事务数据的数据队列，已经通过从站接收到的事务数据 通过桥的主逻辑传递的桥的逻辑，以及响应于事务信息来管理事务和数据队列的控制器，桥被进一步配置为动态地允许单个入队交易的交易数据占据 数据队列中的最大可用空间。

公开(公告)号：US08396996B2

公开(公告)日：2013-03-12

申请号：US13428079

申请日：2012-03-23

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

公开(公告)号：US20100082852A1

公开(公告)日：2010-04-01

申请号：US12286187

申请日：2008-09-29

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/00

CPC分类号： G06F13/122

摘要： In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在处理器中复合来自外围设备的第一写请求的方法，用于响应于第一写请求获得处理器复合的信息，以及将第二写请求从处理器复合体发送到 外围设备包括信息。 描述和要求保护其他实施例。

公开(公告)号：US07145568B2

公开(公告)日：2006-12-05

申请号：US11028595

申请日：2005-01-05

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G09G5/36 ,  G06F15/167 ,  G06F12/00

CPC分类号： G09G5/363 ,  G06F3/14 ,  G06F12/1027 ,  G09G2360/12 ,  G09G2360/125

摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller coupled to the memory controller hub to store graphics data.

摘要翻译： 存储器控制器集线器包括适于对数据执行图形操作的图形子系统和适于存储图形子系统可用于存储图形数据的物理存储器中的位置的高速缓存，并且可用于耦合到存储器控制器集线器的图形控制器以存储图形 数据。

公开(公告)号：US06859208B1

公开(公告)日：2005-02-22

申请号：US09676844

申请日：2000-09-29

申请人： Bryan R. White

发明人： Bryan R. White

IPC分类号： G06F3/153 ,  G06F12/08 ,  G06F12/10 ,  G09G5/36

CPC分类号： G09G5/363 ,  G06F3/14 ,  G06F12/1027 ,  G09G2360/12 ,  G09G2360/125

摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller coupled to the memory controller hub to store graphics data.

公开(公告)号：US20180218530A1

公开(公告)日：2018-08-02

申请号：US15420376

申请日：2017-01-31

申请人： BALAJI VEMBU ,  ALTUG KOKER ,  DAVID PUFFER ,  MURALI RAMADOSS ,  BRYAN R. WHITE ,  HEMA C. NALLURI ,  ADITYA NAVALE

发明人： BALAJI VEMBU ,  ALTUG KOKER ,  DAVID PUFFER ,  MURALI RAMADOSS ,  BRYAN R. WHITE ,  HEMA C. NALLURI ,  ADITYA NAVALE

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06F9/455

CPC分类号： G06F9/45558 ,  G06F9/45541 ,  G06F9/5005

摘要： An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engine to execute a work element using the data identifying a virtual machine or application associated with the work element, wherein different graphics engines are configured to simultaneously execute workloads belonging to different virtual machines or applications.