公开(公告)号：US20090291548A1

公开(公告)日：2009-11-26

申请号：US12124101

申请日：2008-05-20

Applicant: YUAN MING CHANG ,  CHENG DA WU ,  DA YU CHUANG ,  YEN TA CHEN

Inventor： YUAN MING CHANG ,  CHENG DA WU ,  DA YU CHUANG ,  YEN TA CHEN

IPC: H01L21/28

CPC classification number: H01L21/28017 ,  H01L21/32155 ,  H01L21/324

Abstract: A method for preparing a P-type polysilicon gate structure comprises the steps of forming a gate oxide layer on a substrate, forming an N-type polysilicon layer on the gate oxide layer, performing a first implanting process to convert the N-type polysilicon layer into a P-type polysilicon layer, performing a second implanting process to implant P-type dopants into a portion of the P-type polysilicon layer near the interface between the gate oxide layer and the P-type polysilicon layer, and performing a thermal treating process at a predetermined temperature for a predetermined period to complete the P-type polysilicon gate structure.

Abstract translation: 一种制备P型多晶硅栅结构的方法，包括以下步骤：在衬底上形成栅极氧化层，在栅极氧化层上形成N型多晶硅层，进行第一注入工艺以将N型多晶硅层 进入P型多晶硅层，进行第二注入工序，将P型掺杂剂注入到栅极氧化层和P型多晶硅层之间的界面附近的P型多晶硅层的一部分中，进行热处理 在预定温度下处理预定时间以完成P型多晶硅栅极结构。

公开(公告)号：US20100050939A1

公开(公告)日：2010-03-04

申请号：US12198326

申请日：2008-08-26

Applicant: YU PIN HSU ,  YUAN MING CHANG ,  WEI HENG LEE ,  CHENG DA WU

Inventor： YU PIN HSU ,  YUAN MING CHANG ,  WEI HENG LEE ,  CHENG DA WU

IPC: B05C11/00

CPC classification number: H01L21/67253

Abstract: A method for determining the performance of an implanting apparatus comprises the steps of forming a dopant barrier layer on a substrate, forming a target layer on the dopant barrier layer, performing an implanting process by using the implanting apparatus to implant dopants into the target layer such that the target layer becomes conductive, measuring at least one electrical property of the target layer, and determining the performance of the implanting apparatus by taking the electrical property into consideration. In one embodiment of the present invention, the dopant barrier layer is silicon nitride layer, the target layer is a polysilicon layer, and the electrical property is the sheet resistance of the conductive polysilicon layer.

Abstract translation: 一种用于确定植入装置的性能的方法包括以下步骤：在衬底上形成掺杂剂阻挡层，在掺杂剂阻挡层上形成目标层，通过使用注入装置将掺杂剂注入目标层，执行注入过程， 目标层变得导电，测量目标层的至少一个电性质，以及通过考虑电性能来确定植入装置的性能。 在本发明的一个实施例中，掺杂剂阻挡层是氮化硅层，目标层是多晶硅层，电性能是导电多晶硅层的薄层电阻。

公开(公告)号：US20090039295A1

公开(公告)日：2009-02-12

申请号：US12033892

申请日：2008-02-20

Applicant: Hung-Pin Yu ,  Hsueh-Li Chiang ,  Cheng-Da Wu ,  Shiu-Shien Hsheng

Inventor： Hung-Pin Yu ,  Hsueh-Li Chiang ,  Cheng-Da Wu ,  Shiu-Shien Hsheng

IPC: G21F3/00

CPC classification number: H01J37/3171 ,  H01J37/32623 ,  H01J2237/0206 ,  H01J2237/022 ,  H01J2237/026 ,  H01J2237/038 ,  H01J2237/08 ,  H01J2237/16

Abstract: A detachable inner shield suitable for an isolation bushing of an ion implanter is provided. The inner shield is mounted on an inside of the isolation bushing and completely fitting the inside of the isolation bushing.

Abstract translation: 提供了一种适用于离子注入机隔离套管的可拆卸内屏蔽罩。 内屏蔽安装在隔离套管的内侧，并完全安装在隔离套管的内部。

公开(公告)号：US20090298284A1

公开(公告)日：2009-12-03

申请号：US12128434

申请日：2008-05-28

Applicant: TZU LUN CHENG ,  CHENG DA WU ,  DA YU CHUANG ,  WEI HENG LEE

Inventor： TZU LUN CHENG ,  CHENG DA WU ,  DA YU CHUANG ,  WEI HENG LEE

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: A method for preparing an integrated circuit structure performs a deposition process to form a precursor layer on a substrate, and the precursor layer has a phase transition property in a transition temperature region. Subsequently, a first thermal treating process is performed at a first temperature to transform the precursor layer into a polymorphous layer possessing a predetermined crystalline phase, and the first temperature is higher than an upper limit of the temperature of the transition temperature region.

Abstract translation: 制备集成电路结构的方法执行沉积工艺以在衬底上形成前体层，并且前体层在转变温度区域中具有相变特性。 随后，在第一温度下进行第一热处理工艺，以将前体层转变为具有预定结晶相的多晶层，第一温度高于转变温度区域的温度的上限。